Cadence
Senior Principal Emulation Design Engineer
Cadence, San Jose, California, United States, 95199
Senior Principal Emulation Design Engineer
We are seeking a highly skilled design engineer to join our Palladium Solutions Development team, driving the development of full‑system design verification environments. The role focuses on developing, integrating, and validating high‑speed interface subsystems in emulation platforms.
Key Responsibilities
Lead the design and deployment of PHY logic models for emulation platforms including Palladium and Protium.
Develop and maintain end‑to‑end verification environments, encompassing:
System‑level models including microcontrollers, memories, NoC, and high‑speed communication interfaces.
Test case generation.
Interface circuit performance analysis.
Contribute to system prototyping for early bring‑up and validation of full‑system designs.
Collaborate with cross‑functional teams to ensure seamless integration from simulation to emulation.
Optimize designs for multi‑clock domain synchronization, area, and performance, focusing on accuracy vs. runtime trade‑offs.
Drive innovation in emulatable IP solutions and contribute to the evolution of verification methodologies.
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with 7‑15 years of experience.
Strong experience with system‑level design and communication standards such as PCIe, UCIe, Ethernet, UALink, DDR, USB, SPI, JTAG, AMBA protocols.
Proficiency in:
Converting analog mixed signal designs to emulation models while maintaining functional and bit accuracy.
SystemVerilog for synthesizable RTL design.
C and Python for modeling, scripting, and automation.
Laboratory debugging and test case development.
Hands‑on experience with emulation platforms: Palladium, Protium, Zebu, HAPS, Veloci, FPGA.
Deep understanding of verification flows and emulation acceleration techniques.
Preferred Skills
Experience building emulatable AVIP solutions.
Familiarity with end‑to‑end verification environments from simulation through emulation.
Experience in system prototyping and bring‑up.
Strong analytical and problem‑solving skills.
Excellent communication and leadership abilities.
Salary & Benefits The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Our benefits programs include paid vacation and holidays, 401(k) plan with employer match, employee stock purchase plan, medical, dental, vision plans, and more.
Location: Sunnyvale, CA. Employment type: Full‑time.
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Key Responsibilities
Lead the design and deployment of PHY logic models for emulation platforms including Palladium and Protium.
Develop and maintain end‑to‑end verification environments, encompassing:
System‑level models including microcontrollers, memories, NoC, and high‑speed communication interfaces.
Test case generation.
Interface circuit performance analysis.
Contribute to system prototyping for early bring‑up and validation of full‑system designs.
Collaborate with cross‑functional teams to ensure seamless integration from simulation to emulation.
Optimize designs for multi‑clock domain synchronization, area, and performance, focusing on accuracy vs. runtime trade‑offs.
Drive innovation in emulatable IP solutions and contribute to the evolution of verification methodologies.
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with 7‑15 years of experience.
Strong experience with system‑level design and communication standards such as PCIe, UCIe, Ethernet, UALink, DDR, USB, SPI, JTAG, AMBA protocols.
Proficiency in:
Converting analog mixed signal designs to emulation models while maintaining functional and bit accuracy.
SystemVerilog for synthesizable RTL design.
C and Python for modeling, scripting, and automation.
Laboratory debugging and test case development.
Hands‑on experience with emulation platforms: Palladium, Protium, Zebu, HAPS, Veloci, FPGA.
Deep understanding of verification flows and emulation acceleration techniques.
Preferred Skills
Experience building emulatable AVIP solutions.
Familiarity with end‑to‑end verification environments from simulation through emulation.
Experience in system prototyping and bring‑up.
Strong analytical and problem‑solving skills.
Excellent communication and leadership abilities.
Salary & Benefits The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Our benefits programs include paid vacation and holidays, 401(k) plan with employer match, employee stock purchase plan, medical, dental, vision plans, and more.
Location: Sunnyvale, CA. Employment type: Full‑time.
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