ASIC Clocks Design Engineer - New Grad (Hybrid, Equity)

A leading technology firm is looking for an ASIC Clocks Design Engineer. This position requires a BS in Electrical Engineering and emphasizes collaboration with various teams to design and optimize GPU/CPU clocks. Responsibilities include architecting clock domains, addressing design constraints, and improving performance. The ideal candidate has experience in RTL design, logic optimization, and strong interpersonal skills. The position offers a competitive salary range between 108,000 and 184,000 USD for Level 2, and 136,000 to 212,750 USD for Level 3, with hybrid work options. #J-18808-Ljbffr