MatX
MatX is looking for a motivated Signal & Power Integrity (Si/PI) Engineer to join our hardware engineering team to solve cutting‑edge technical challenges in high‑performance AI chips and systems.
In this role, you’ll work with senior‑level engineers to design 224G SerDes channels, including silicon interposer, substrate, extra low‑loss PCB and high‑speed connectors to ensure reliable high‑speed electrical performance. You will also work on designing the power delivery networks to ensure both DC and transient power integrity for accelerator chips and other critical components.
What You’ll Do Here
Signal Integrity (SI)
for interfaces of PCIe 6/7, 224‑Gbps PAM4, HBM and D2D
Optimize interconnects from uBump to C4 bump, substrate uvia, and PTH via and PCB via to minimize the insertion loss Channel Modeling and simulation for interfaces of PCIe 6/7, 224‑Gbps PAM4, HBM, D2D based on IP electrical spec and physical design rules Perform channel analysis using S‑parameters, eye‑diagram, and BER estimation, insertion loss/crosstalk budgets Generate physical design rules for interposer LSI, substrate and PCB layout Power Integrity (PI)
Design and simulate PDN (Power Delivery Networks) from VRM to die/package: impedance targets, decoupling strategy, and resonances Perform frequency‑domain impedance and time‑domain transient analysis (AC/DC) Evaluate DC IR drop and transient voltage stability under dynamic loading Measurement & Validation
Correlate simulation to lab results using
VNA, TDR, and oscilloscope
measurements Support bring‑up and debug of boards/modules exhibiting SI/PI anomalies Conduct high‑speed SerDes bench BER testing to ensure channel performance Perform power transient and noise measurements with oscilloscope Who You Are BSEE or MSEE in Electrical Engineering, Applied Physics, or related field 5–8 years of experience in SI/PI engineering or related high‑speed hardware design Proficiency with industry tools such as Ansys HFSS/Siwave, Keysight ADS, Cadence Clarity and Sigrity, Keysight PathWave, PowerSI, SPICE, etc Familiar with PCB design and substrate design, via optimization and modeling Strong understanding of return‑path design, crosstalk mitigation, and PDN target impedance concepts Hands‑on lab experience with oscilloscopes, VNAs, and power measurement equipment This is a hybrid role that will require you to work from our Mountain View, CA office 3 days a week on Tuesday through Thursday Bonus Points If You Have Experience with
224 Gb/s interconnects
and CoWoS‑L interposer design Scripting skills (Python, MATLAB, TCL) for automation and data processing. Familiarity with high‑speed interface protocols (Ethernet/PCIe/HBM) and ability to perform channel analysis based on relevant specifications, such as COM analysis for 224G SerDes What We Offer A stake in our success
A cash/equity mix that fits your needs, and an option to do early exercise Health & Wellness
Company subsidized Health, Dental, and Vision insurance; Flexible Savings Accounts (FSA), and a Health Savings Account (HSA) with a lump sum company contribution Financial Wellbeing
Choose from Guardian 401K and/or Roth IRA (or both) and receive a 5% company contribution, even if you don’t! Plus 100% paid Life and long‑term disability insurances. Time To Recharge
4 weeks PTO (accrued), 12 holidays & 3 weeks remote/flexible work per year Mental Wellbeing
100% paid mental health benefit via SpringHealth and Guardian EAP Professional Development
$1,500 yearly towards conferences, courses, and other learning Team Connection
Team lunches, quarterly off‑sites, and regular town halls Commute On Us We’ll pay for your commute (up to 1 hr) to get work done during your commute! MatX E[x]tras
$50/month to use on the perks you care about most Remote Perks
We work remotely on Monday & Friday, home‑tech setup & remote wifi expensing Support to Parents
Up to 12 weeks of paid parental leave & 10 weeks of pregnancy disability leave, regardless of path to parenthood. Plus Maven reproductive health & parental benefit As part of our dedication to the diversity of our team and our focus on creating an inviting and inclusive work experience, MatX is committed to a policy of Equal Employment Opportunity and will not discriminate against an applicant or employee on the basis of race, color, religion, creed, national origin or ancestry, sex, gender, gender identity, gender expression, sexual orientation, age, physical or mental disability, medical condition, marital/domestic partner status, military and veteran status, genetic information or any other legally recognized protected basis under federal, state or local laws, regulations or ordinances. All candidates must be authorized to work in the United States and work from our offices in Mountain View Tuesdays‑Thursdays. This position requires access to information that is subject to U.S. export controls. This offer of employment is contingent upon the applicant's capacity to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities. MatX does not accept unsolicited resumes from individual recruiters or third‑party recruiting agencies in response to job postings. No fee will be paid to third parties who submit unsolicited candidates directly to our hiring managers or People team and any resumes submitted are deemed to be the property of MatX.
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for interfaces of PCIe 6/7, 224‑Gbps PAM4, HBM and D2D
Optimize interconnects from uBump to C4 bump, substrate uvia, and PTH via and PCB via to minimize the insertion loss Channel Modeling and simulation for interfaces of PCIe 6/7, 224‑Gbps PAM4, HBM, D2D based on IP electrical spec and physical design rules Perform channel analysis using S‑parameters, eye‑diagram, and BER estimation, insertion loss/crosstalk budgets Generate physical design rules for interposer LSI, substrate and PCB layout Power Integrity (PI)
Design and simulate PDN (Power Delivery Networks) from VRM to die/package: impedance targets, decoupling strategy, and resonances Perform frequency‑domain impedance and time‑domain transient analysis (AC/DC) Evaluate DC IR drop and transient voltage stability under dynamic loading Measurement & Validation
Correlate simulation to lab results using
VNA, TDR, and oscilloscope
measurements Support bring‑up and debug of boards/modules exhibiting SI/PI anomalies Conduct high‑speed SerDes bench BER testing to ensure channel performance Perform power transient and noise measurements with oscilloscope Who You Are BSEE or MSEE in Electrical Engineering, Applied Physics, or related field 5–8 years of experience in SI/PI engineering or related high‑speed hardware design Proficiency with industry tools such as Ansys HFSS/Siwave, Keysight ADS, Cadence Clarity and Sigrity, Keysight PathWave, PowerSI, SPICE, etc Familiar with PCB design and substrate design, via optimization and modeling Strong understanding of return‑path design, crosstalk mitigation, and PDN target impedance concepts Hands‑on lab experience with oscilloscopes, VNAs, and power measurement equipment This is a hybrid role that will require you to work from our Mountain View, CA office 3 days a week on Tuesday through Thursday Bonus Points If You Have Experience with
224 Gb/s interconnects
and CoWoS‑L interposer design Scripting skills (Python, MATLAB, TCL) for automation and data processing. Familiarity with high‑speed interface protocols (Ethernet/PCIe/HBM) and ability to perform channel analysis based on relevant specifications, such as COM analysis for 224G SerDes What We Offer A stake in our success
A cash/equity mix that fits your needs, and an option to do early exercise Health & Wellness
Company subsidized Health, Dental, and Vision insurance; Flexible Savings Accounts (FSA), and a Health Savings Account (HSA) with a lump sum company contribution Financial Wellbeing
Choose from Guardian 401K and/or Roth IRA (or both) and receive a 5% company contribution, even if you don’t! Plus 100% paid Life and long‑term disability insurances. Time To Recharge
4 weeks PTO (accrued), 12 holidays & 3 weeks remote/flexible work per year Mental Wellbeing
100% paid mental health benefit via SpringHealth and Guardian EAP Professional Development
$1,500 yearly towards conferences, courses, and other learning Team Connection
Team lunches, quarterly off‑sites, and regular town halls Commute On Us We’ll pay for your commute (up to 1 hr) to get work done during your commute! MatX E[x]tras
$50/month to use on the perks you care about most Remote Perks
We work remotely on Monday & Friday, home‑tech setup & remote wifi expensing Support to Parents
Up to 12 weeks of paid parental leave & 10 weeks of pregnancy disability leave, regardless of path to parenthood. Plus Maven reproductive health & parental benefit As part of our dedication to the diversity of our team and our focus on creating an inviting and inclusive work experience, MatX is committed to a policy of Equal Employment Opportunity and will not discriminate against an applicant or employee on the basis of race, color, religion, creed, national origin or ancestry, sex, gender, gender identity, gender expression, sexual orientation, age, physical or mental disability, medical condition, marital/domestic partner status, military and veteran status, genetic information or any other legally recognized protected basis under federal, state or local laws, regulations or ordinances. All candidates must be authorized to work in the United States and work from our offices in Mountain View Tuesdays‑Thursdays. This position requires access to information that is subject to U.S. export controls. This offer of employment is contingent upon the applicant's capacity to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities. MatX does not accept unsolicited resumes from individual recruiters or third‑party recruiting agencies in response to job postings. No fee will be paid to third parties who submit unsolicited candidates directly to our hiring managers or People team and any resumes submitted are deemed to be the property of MatX.
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