LanceSoft, Inc.
Application Specific Integrated Circuit Design Engineer
LanceSoft, Inc., Austin, Texas, us, 78716
Application Specific Integrated Circuit Design Engineer
Application Specific Integrated Circuit Design Engineer
This range is provided by LanceSoft, Inc.. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Base pay range
$75.00/hr - $95.00/hr Direct message the job poster from LanceSoft, Inc. Lead-US Staffing(Semiconductor)::Hiring - Physical design Engineers II Design Verification Engineers II DFT Engineers II Embedded/Firmware EngineerII…
> THE ROLE: > > > > The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologies in parallel. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs. > > > > THE PERSON: > > You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. > > > > KEY RESPONSIBILITIES: > > • RTL design for memory I/O > > • PHY Digital Architecture development from pathfinding, coding, verification to physical implementation > > • PHY link layer design, implementation & verification with Analog and System architect. > > > • Digital design and RTL coding > > • Timing Synthesis & Drive Physical implementation > > • Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified > > • Build the unit tests > > • Debug design failures to determine the root cause; work with DV and firmware engineers to resolve design defects and correct any test issues > > > > > > PREFERRED EXPERIENCE: > > > • Proficient in debugging firmware and RTL code using simulation tools > > • Proficient in using UVM testbenches and working in Linux and Windows environments > > • Experienced with Verilog, System Verilog, C, and C++ > > • Excellent knowledge of Verilog, System Verilog and a scripting language; experience with Python, Perl and TCL is a plus > > • Knowledge of clocking architectures, synchronization, and CDC methodology > > • SERDES, DDR, Memory Controller, or MAC Design experience is preferred > > • Strong understanding of computer organization/architecture. > > • Mixed signal RTL experience is a plus > > > > ACADEMIC CREDENTIALS: > > • Bachelors or Masters degree in computer engineering/Electrical Engineering Job Description: Prefer experience with PSS language and UVM. JOB DUTIES: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation. Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects. Be familiar with hardware modeling and/or assertion-based verification methods.EXPERIENCE AND EDUCATION:5 or more years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting;Strong background in PSS/UVM/SystemVerilog; Experience in Verilog/SystemVerilog/SystemC, preferred;Experience in C/Verilog environment using DPI/PLI, preferred;Strong analytical skills and attention to detail;Excellent written and communication skills Employee Benefits: At LanceSoft, full time regular employees who work a minimum of 30 hours a week or more are entitled to the following benefits: • Four options of medical Insurance • Dental and Vision Insurance • Critical Illness Insurance • Voluntary Permanent Life Insurance • Other Employee Perks About LanceSoft LanceSoft is rated as one of the largest staffing firms in the US by SIA. Our mission is to establish global cross-culture human connections that further the careers of our employees and strengthen the businesses of our clients. We are driven to use the power of our global network to connect businesses with the right people, and people with the right businesses without bias. We provide Global Workforce Solutions with a human touch. EEO Employer LanceSoft is a certified Minority Business Enterprise (MBE) and an equal opportunity employer. We prohibit discrimination and harassment of any kind based on race, color, sex, religion, sexual orientation, national origin, disability, genetic information, pregnancy, or any other protected characteristic as outlined by federal, state, or local laws. This policy applies to all employment practices within our organization, including hiring, recruiting, promotion, termination, layoff, recall, leave of absence, compensation, benefits, training, and apprenticeship. LanceSoft makes hiring decisions based solely on qualifications, merit, and business needs at the time. Want to read more about LanceSoft? Click here to visit our website - www.lancesoft.com Seniority level
Seniority level Mid-Senior level Employment type
Employment type Contract Job function
Industries Manufacturing Referrals increase your chances of interviewing at LanceSoft, Inc. by 2x Get notified about new Application Specific Integrated Circuit Design Engineer jobs in
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Application Specific Integrated Circuit Design Engineer
This range is provided by LanceSoft, Inc.. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Base pay range
$75.00/hr - $95.00/hr Direct message the job poster from LanceSoft, Inc. Lead-US Staffing(Semiconductor)::Hiring - Physical design Engineers II Design Verification Engineers II DFT Engineers II Embedded/Firmware EngineerII…
> THE ROLE: > > > > The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologies in parallel. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs. > > > > THE PERSON: > > You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. > > > > KEY RESPONSIBILITIES: > > • RTL design for memory I/O > > • PHY Digital Architecture development from pathfinding, coding, verification to physical implementation > > • PHY link layer design, implementation & verification with Analog and System architect. > > > • Digital design and RTL coding > > • Timing Synthesis & Drive Physical implementation > > • Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified > > • Build the unit tests > > • Debug design failures to determine the root cause; work with DV and firmware engineers to resolve design defects and correct any test issues > > > > > > PREFERRED EXPERIENCE: > > > • Proficient in debugging firmware and RTL code using simulation tools > > • Proficient in using UVM testbenches and working in Linux and Windows environments > > • Experienced with Verilog, System Verilog, C, and C++ > > • Excellent knowledge of Verilog, System Verilog and a scripting language; experience with Python, Perl and TCL is a plus > > • Knowledge of clocking architectures, synchronization, and CDC methodology > > • SERDES, DDR, Memory Controller, or MAC Design experience is preferred > > • Strong understanding of computer organization/architecture. > > • Mixed signal RTL experience is a plus > > > > ACADEMIC CREDENTIALS: > > • Bachelors or Masters degree in computer engineering/Electrical Engineering Job Description: Prefer experience with PSS language and UVM. JOB DUTIES: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation. Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects. Be familiar with hardware modeling and/or assertion-based verification methods.EXPERIENCE AND EDUCATION:5 or more years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting;Strong background in PSS/UVM/SystemVerilog; Experience in Verilog/SystemVerilog/SystemC, preferred;Experience in C/Verilog environment using DPI/PLI, preferred;Strong analytical skills and attention to detail;Excellent written and communication skills Employee Benefits: At LanceSoft, full time regular employees who work a minimum of 30 hours a week or more are entitled to the following benefits: • Four options of medical Insurance • Dental and Vision Insurance • Critical Illness Insurance • Voluntary Permanent Life Insurance • Other Employee Perks About LanceSoft LanceSoft is rated as one of the largest staffing firms in the US by SIA. Our mission is to establish global cross-culture human connections that further the careers of our employees and strengthen the businesses of our clients. We are driven to use the power of our global network to connect businesses with the right people, and people with the right businesses without bias. We provide Global Workforce Solutions with a human touch. EEO Employer LanceSoft is a certified Minority Business Enterprise (MBE) and an equal opportunity employer. We prohibit discrimination and harassment of any kind based on race, color, sex, religion, sexual orientation, national origin, disability, genetic information, pregnancy, or any other protected characteristic as outlined by federal, state, or local laws. This policy applies to all employment practices within our organization, including hiring, recruiting, promotion, termination, layoff, recall, leave of absence, compensation, benefits, training, and apprenticeship. LanceSoft makes hiring decisions based solely on qualifications, merit, and business needs at the time. Want to read more about LanceSoft? Click here to visit our website - www.lancesoft.com Seniority level
Seniority level Mid-Senior level Employment type
Employment type Contract Job function
Industries Manufacturing Referrals increase your chances of interviewing at LanceSoft, Inc. by 2x Get notified about new Application Specific Integrated Circuit Design Engineer jobs in
San Jose, CA . ASIC/SOC Silicon Physical Design Engineer
Mountain View, CA $120,000.00-$400,000.00 7 months ago Senior ASIC FrontEnd (RTL) Design Engineer
Sunnyvale, CA $114,000.00-$166,000.00 2 weeks ago Senior ASIC Physical Design Engineer - High Performance Designs
Sunnyvale, CA $142,000.00-$203,000.00 2 weeks ago Senior ASIC Design Verification Engineer (Hardware)
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Digital Design Engineer, Reality Labs Silicon AI Research
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Sunnyvale, CA $142,000.00-$203,000.00 1 week ago Sunnyvale, CA $114,000.00-$166,000.00 2 weeks ago Senior ASIC Physical Design and Timing Engineer
Santa Clara, CA $136,000.00-$264,500.00 3 days ago Low Power ASIC Engineer - New College Grad 2025
We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.
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