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Job DescriptionJob DescriptionOur client is a fast-growing, multi-disciplined, privately owned small business that develops and delivers affordable, reliable, high-performance products.
Summary
Our client is seeking a Senior HDL Systems Architect to help shape the future of our advanced RF systems. This isnt just a hands-on FPGA development role. Were looking for someone who has grown from a strong HDL developer into a strategic systems thinker - someone who can look at the big picture, understand tradeoffs, and lead architectural design.
Youll work closely with multidisciplinary teams to architect, develop, and refine high-performance digital systems across diverse RF and antenna applications. You should thrive in a collaborative, engineering-driven culture and enjoy working in a fast-paced R&D environment where you have real impact on fielded products.
What Youll Do
Architect and implement system-level digital signal processing and control solutions using HDL (Verilog, VHDL, or similar).
Lead design decisions from initial requirements through to system integration and validation.
Collaborate with RF, embedded software, and hardware teams to design cohesive and efficient systems.
Provide mentorship to junior HDL developers and help drive technical excellence across the team.
Own design documentation, simulation, and testing strategies at both the module and system level.
Evaluate trade-offs and component selection during architectural design phases.
Work with build systems and Linux environments to support hardware bring-up and integrations
Qualifications
Required Education and Experience
U.S. Citizenship
and ability to obtain a U.S. Security Clearance.
Bachelors degree in Electrical Engineering, Computer Engineering, or a related field (Masters ).
3+ years of experience in FPGA development using Verilog/VHDL
Demonstrated experience architecting complex digital systems, not just implementing isolated blocks.
Deep understanding of signal processing, system interfaces, and timing constraints.
Experience working with high-speed serial protocols (PCIe, SPI, I2C, AXI, Aurora, JESD, etc.).
Familiarity with RF system concepts and how HDL integrates with analog hardware.
Experience
Python, C/C++, or other scripting/ experience that supports test and tooling development.
Linux development (user-space, device drivers, or build systems like Yocto or Petalinux).
Simulation tools and testbenches (ModelSim, Vivado, etc.).
Hardware experience - schematic capture, board bring-up, or lab test/debug work.
Tools like Spade or Veryl for system modeling or HDL .
Benefits Summary
Our client offers all employees four weeks of PTO each year, flexible scheduling, hybrid work, tuition reimbursement, up to 6% 401(k) match, and 100% employer-paid healthcare, dental, and vision plans.
Work Environment
This job operates in a professional office and laboratory. This role routinely uses laboratory equipment such as vector network analyzers, signal generators, and spectrum analyzers.
Position Type/Expected Hours of Work
This is a full-time position at 40 hours per week. Typical office hours include Monday-Friday, 8:00am-5:00pm, however these hours will vary based on workload and the managers discretion. This job may require more than 40 hours of work per week as the need arises.
Travel
Minimal travel (
Physical Demands
While performing the duties of this job, you will be regularly required to talk or hear. Specific vision abilities required by this job include close vision and ability to adjust focus. This would require the ability to lift lab equipment, open cabinets, and bend or stand on a stool as necessary. Reasonable accommodations may be made to enable individuals with disabilities to perform essential functions.
Other Duties
Please note this job description is not designed to cover or contain a comprehensive listing of activities, duties or responsibilities that are required of the employee for this job. Duties, responsibilities, and activities may change at any time with or without notice.
This position has no direct supervisory responsibilities.
AAP/EEO Statement
Our client does not discriminate based on , , , , , sex, , , , genetic information, military or veteran status, or any other status protected by law or regulation. It is their intention that all qualified applicants are given equal opportunity and that employment decisions be based on job-related factors.
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Summary
Our client is seeking a Senior HDL Systems Architect to help shape the future of our advanced RF systems. This isnt just a hands-on FPGA development role. Were looking for someone who has grown from a strong HDL developer into a strategic systems thinker - someone who can look at the big picture, understand tradeoffs, and lead architectural design.
Youll work closely with multidisciplinary teams to architect, develop, and refine high-performance digital systems across diverse RF and antenna applications. You should thrive in a collaborative, engineering-driven culture and enjoy working in a fast-paced R&D environment where you have real impact on fielded products.
What Youll Do
Architect and implement system-level digital signal processing and control solutions using HDL (Verilog, VHDL, or similar).
Lead design decisions from initial requirements through to system integration and validation.
Collaborate with RF, embedded software, and hardware teams to design cohesive and efficient systems.
Provide mentorship to junior HDL developers and help drive technical excellence across the team.
Own design documentation, simulation, and testing strategies at both the module and system level.
Evaluate trade-offs and component selection during architectural design phases.
Work with build systems and Linux environments to support hardware bring-up and integrations
Qualifications
Required Education and Experience
U.S. Citizenship
and ability to obtain a U.S. Security Clearance.
Bachelors degree in Electrical Engineering, Computer Engineering, or a related field (Masters ).
3+ years of experience in FPGA development using Verilog/VHDL
Demonstrated experience architecting complex digital systems, not just implementing isolated blocks.
Deep understanding of signal processing, system interfaces, and timing constraints.
Experience working with high-speed serial protocols (PCIe, SPI, I2C, AXI, Aurora, JESD, etc.).
Familiarity with RF system concepts and how HDL integrates with analog hardware.
Experience
Python, C/C++, or other scripting/ experience that supports test and tooling development.
Linux development (user-space, device drivers, or build systems like Yocto or Petalinux).
Simulation tools and testbenches (ModelSim, Vivado, etc.).
Hardware experience - schematic capture, board bring-up, or lab test/debug work.
Tools like Spade or Veryl for system modeling or HDL .
Benefits Summary
Our client offers all employees four weeks of PTO each year, flexible scheduling, hybrid work, tuition reimbursement, up to 6% 401(k) match, and 100% employer-paid healthcare, dental, and vision plans.
Work Environment
This job operates in a professional office and laboratory. This role routinely uses laboratory equipment such as vector network analyzers, signal generators, and spectrum analyzers.
Position Type/Expected Hours of Work
This is a full-time position at 40 hours per week. Typical office hours include Monday-Friday, 8:00am-5:00pm, however these hours will vary based on workload and the managers discretion. This job may require more than 40 hours of work per week as the need arises.
Travel
Minimal travel (
Physical Demands
While performing the duties of this job, you will be regularly required to talk or hear. Specific vision abilities required by this job include close vision and ability to adjust focus. This would require the ability to lift lab equipment, open cabinets, and bend or stand on a stool as necessary. Reasonable accommodations may be made to enable individuals with disabilities to perform essential functions.
Other Duties
Please note this job description is not designed to cover or contain a comprehensive listing of activities, duties or responsibilities that are required of the employee for this job. Duties, responsibilities, and activities may change at any time with or without notice.
This position has no direct supervisory responsibilities.
AAP/EEO Statement
Our client does not discriminate based on , , , , , sex, , , , genetic information, military or veteran status, or any other status protected by law or regulation. It is their intention that all qualified applicants are given equal opportunity and that employment decisions be based on job-related factors.
#J-18808-Ljbffr