AMD
Analog Design Engineer – AMD
Join to apply for the Analog Design Engineer role at AMD.
Base Pay Range $157,120.00/yr - $235,680.00/yr
Location Santa Clara, CA
Overview At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover that our culture is the real differentiator. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
The Role We are searching for an experienced Circuit Design Engineer to join the fast-growing PLL design team, responsible for defining, specifying, and implementing current and future advanced PLL IPs powering AMD products.
The Person
Solid knowledge of Mixed Signal Circuit Design in FinFET technology specifically in PLLs and associated subblocks including VCO, charge‑pump, dividers, state machines, LDO, feedback and compensation techniques, bandgap, TDC, interpolator circuits, high‑speed buffers, etc.
Solid knowledge of industry‑standard tools and practices for analog circuit design.
Good knowledge in Physical design, STA, methodology scripts (Tcl), knowledge on Perl, Python.
Quality‑oriented mindset.
Strong and effective communication skills and team spirit.
Key Responsibilities
Design complex building blocks of a PLL including architecture development and transistor‑level circuit design.
Run pre‑tapeout verification flows to confirm design meets performance, power, reliability and timing requirements.
Work closely with mask design engineers to deliver the physical design as well as define production/bench‑level test plans with post‑silicon characterization groups for silicon evaluation to ensure interlocked and high‑quality execution.
Lead and mentor junior engineers.
Preferred Experience
Strong experience in the semiconductor industry.
Experience in FinFET & Dual Patterning nodes such as 16/14/10/7 nm.
Hands‑on design experience in performance analog and hybrid Phase Locked Loops, analog‑to‑digital (ADC), digital‑to‑analog (DAC) data converters, VCO, LDO, bandgap, charge pump, op‑amps, interpolator circuits.
Experience with Digital PLL techniques, TDC or DSP and control theory experience related to digital PLLs, Dual charge‑pump PLL designs, Fractional‑N PLLs, spread‑spectra PLLs is a plus.
Proficient with Cadence custom circuit design tools like ADE‑L and ADE‑XL and running Monte‑Carlo, noise, aging, EM and IR drop simulations and stability analysis. Helic/EMX is a plus.
Good experience with simulation tools such as Spectre, Hspice, AFS, MATLAB, SystemVerilog, Python.
Capable of understanding DRC and LVS results with verification tools (Calibre, ICV, or similar).
Proficiency in scripting languages like Perl, Python, MATLAB is a plus.
Able to work effectively in a team, with good interpersonal skills, enthusiasm and positive energy.
Possess strong analytical/problem‑solving skills and pronounced attention to details.
Must be a self‑starter, and able to independently drive tasks to completion.
Academic Credentials
Master’s in Electrical Engineering or equivalent preferred.
Benefits Benefits offered are described: AMD benefits at a glance.
EEO Statement AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal‑opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
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Base Pay Range $157,120.00/yr - $235,680.00/yr
Location Santa Clara, CA
Overview At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover that our culture is the real differentiator. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
The Role We are searching for an experienced Circuit Design Engineer to join the fast-growing PLL design team, responsible for defining, specifying, and implementing current and future advanced PLL IPs powering AMD products.
The Person
Solid knowledge of Mixed Signal Circuit Design in FinFET technology specifically in PLLs and associated subblocks including VCO, charge‑pump, dividers, state machines, LDO, feedback and compensation techniques, bandgap, TDC, interpolator circuits, high‑speed buffers, etc.
Solid knowledge of industry‑standard tools and practices for analog circuit design.
Good knowledge in Physical design, STA, methodology scripts (Tcl), knowledge on Perl, Python.
Quality‑oriented mindset.
Strong and effective communication skills and team spirit.
Key Responsibilities
Design complex building blocks of a PLL including architecture development and transistor‑level circuit design.
Run pre‑tapeout verification flows to confirm design meets performance, power, reliability and timing requirements.
Work closely with mask design engineers to deliver the physical design as well as define production/bench‑level test plans with post‑silicon characterization groups for silicon evaluation to ensure interlocked and high‑quality execution.
Lead and mentor junior engineers.
Preferred Experience
Strong experience in the semiconductor industry.
Experience in FinFET & Dual Patterning nodes such as 16/14/10/7 nm.
Hands‑on design experience in performance analog and hybrid Phase Locked Loops, analog‑to‑digital (ADC), digital‑to‑analog (DAC) data converters, VCO, LDO, bandgap, charge pump, op‑amps, interpolator circuits.
Experience with Digital PLL techniques, TDC or DSP and control theory experience related to digital PLLs, Dual charge‑pump PLL designs, Fractional‑N PLLs, spread‑spectra PLLs is a plus.
Proficient with Cadence custom circuit design tools like ADE‑L and ADE‑XL and running Monte‑Carlo, noise, aging, EM and IR drop simulations and stability analysis. Helic/EMX is a plus.
Good experience with simulation tools such as Spectre, Hspice, AFS, MATLAB, SystemVerilog, Python.
Capable of understanding DRC and LVS results with verification tools (Calibre, ICV, or similar).
Proficiency in scripting languages like Perl, Python, MATLAB is a plus.
Able to work effectively in a team, with good interpersonal skills, enthusiasm and positive energy.
Possess strong analytical/problem‑solving skills and pronounced attention to details.
Must be a self‑starter, and able to independently drive tasks to completion.
Academic Credentials
Master’s in Electrical Engineering or equivalent preferred.
Benefits Benefits offered are described: AMD benefits at a glance.
EEO Statement AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal‑opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
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