Intel Corporation
DFT Design Engineer – Intel Corporation
Do Something Wonderful! Intel puts the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world‑changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow.
Responsibilities
Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN).
Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in‑system test/BIST).
Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE).
Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT.
Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals as well as design integrity for physical implementation.
Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications.
Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high‑quality integration of the IP block.
Collaborates with post‑silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements required in design and validation.
Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.
Qualifications Minimum Qualifications
Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 4+ years of relevant experience
Master’s degree in the same fields with 3+ years of relevant experience
PhD in the same fields with 6+ months of relevant experience
Relevant Work Experience
Experience with DFT Array Test including MBIST or Scan/ATPG or DFT Verification
Preferred Qualifications
Expertise in Tessent DFT tool
Expertise in Primetime especially in DFT constraints
Expertise in quality checks such as Lint, VCLP, CDC/RDC, LEC, Spyglass DFT
Job Type Experienced Hire
Shift Shift 1 (United States of America)
Primary Location US, California, Santa Clara
Additional Locations US, Oregon, Hillsboro US, Texas, Austin
Business Group At the Data Center Group (DCG), we are committed to delivering exceptional products and delighting our customers. We offer both broad‑market Xeon‑based solutions and custom x86‑based products, ensuring tailored innovation for diverse needs across general‑purpose compute, web services, HPC, and AI‑accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload‑driven leadership products and close collaboration with our partners.
Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as benefit programs which include health, retirement, and vacation. Find more information about all of our amazing benefits here: https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003
Salary Range Annual Salary Range for jobs which could be performed in the US: 139,710.00 USD - 262,680.00 USD. The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model This role will require an on‑site presence.
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Do Something Wonderful! Intel puts the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world‑changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow.
Responsibilities
Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN).
Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in‑system test/BIST).
Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE).
Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT.
Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals as well as design integrity for physical implementation.
Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications.
Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high‑quality integration of the IP block.
Collaborates with post‑silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements required in design and validation.
Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.
Qualifications Minimum Qualifications
Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 4+ years of relevant experience
Master’s degree in the same fields with 3+ years of relevant experience
PhD in the same fields with 6+ months of relevant experience
Relevant Work Experience
Experience with DFT Array Test including MBIST or Scan/ATPG or DFT Verification
Preferred Qualifications
Expertise in Tessent DFT tool
Expertise in Primetime especially in DFT constraints
Expertise in quality checks such as Lint, VCLP, CDC/RDC, LEC, Spyglass DFT
Job Type Experienced Hire
Shift Shift 1 (United States of America)
Primary Location US, California, Santa Clara
Additional Locations US, Oregon, Hillsboro US, Texas, Austin
Business Group At the Data Center Group (DCG), we are committed to delivering exceptional products and delighting our customers. We offer both broad‑market Xeon‑based solutions and custom x86‑based products, ensuring tailored innovation for diverse needs across general‑purpose compute, web services, HPC, and AI‑accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload‑driven leadership products and close collaboration with our partners.
Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as benefit programs which include health, retirement, and vacation. Find more information about all of our amazing benefits here: https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003
Salary Range Annual Salary Range for jobs which could be performed in the US: 139,710.00 USD - 262,680.00 USD. The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model This role will require an on‑site presence.
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