Remote ASIC Physical Design Lead — Tapeout Expert

A leading semiconductor firm seeks an experienced ASIC Physical Design Lead to drive complex SoC design implementations from RTL handoff through tapeout. Candidates must have 10+ years of ASIC Physical Design experience, proven tape-out ownership, and strong leadership capabilities. This remote role requires deep knowledge in Floorplanning, Place & Route, and proficiency with Cadence or Synopsys toolchains. Ideal candidates will translate product requirements into actionable design goals and deliver solutions across advanced technology nodes. #J-18808-Ljbffr