Vista Applied Solutions Group Inc
Semiconductor Packaging engineer
Vista Applied Solutions Group Inc, Santa Clara, California, us, 95053
This role is highly specialized in semiconductor packaging design, requiring strong EDA tool proficiency and knowledge of advanced packaging technologies.
Responsibilities
Tools & Knowledge:
Mentor/Siemens and Cadence tools (especially for Package Layout Automation - PLA).
Technical Expertise:
Understanding of substrate manufacturing Design Rules and Assembly Rules.
Familiarity with SIPI (Signal Integrity & Power Integrity) Rules.
Tasks:
Perform point-to-point connections.
Run DRC (Design Rule Checks), identify root causes, and fix issues.
Execute design based on provided schematics, including component placement and constraint setup.
Seniority Level Mid‑Senior level
Employment Type Contract
Job Function Information Technology
Industries IT Services and IT Consulting
Location San Jose, CA
Salary US$138,720.00 – 208,080.00
#J-18808-Ljbffr
Responsibilities
Tools & Knowledge:
Mentor/Siemens and Cadence tools (especially for Package Layout Automation - PLA).
Technical Expertise:
Understanding of substrate manufacturing Design Rules and Assembly Rules.
Familiarity with SIPI (Signal Integrity & Power Integrity) Rules.
Tasks:
Perform point-to-point connections.
Run DRC (Design Rule Checks), identify root causes, and fix issues.
Execute design based on provided schematics, including component placement and constraint setup.
Seniority Level Mid‑Senior level
Employment Type Contract
Job Function Information Technology
Industries IT Services and IT Consulting
Location San Jose, CA
Salary US$138,720.00 – 208,080.00
#J-18808-Ljbffr