Vivid Technology
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This well-funded (Series B) start-up is building a new class of high-resolution perception sensing technology for ADAS and autonomous driving.
Seeking an IC Packaging Engineer to lead the development and delivery of advanced multi-chip packaging solutions for THz-system RFIC, SoC, and high-speed digital applications. This high-impact role combines technical leadership, hands‑on package design, and collaboration with OSATs, with a focus on 2.5D and interposer‑based architectures. The ideal candidate will have deep expertise in package physical design (layout, stack‑ups, DFM, SI/PI), thermal‑mechanical modelling, and high‑volume manufacturing and test, enabling them to execute designs directly or guide junior engineers toward production‑ready solutions.
Responsibilities
Technical leadership, guiding the design and execution of advanced IC packages for multi‑chip RFIC/SoC integration.
Develop 2.5D packages with UCIe chip‑to‑chip interconnects and interposer‑based solutions.
Work on single‑sided and double‑sided RDL designs and on‑package RF antenna structures.
Co‑optimize package designs for signal integrity, thermal, and mechanical performance in collaboration with RFIC, digital, and system engineers.
Drive material selection, DFM, and reliability qualification to meet automotive‑grade requirements (AEC‑Q).
Perform stress, warpage, and thermal simulations using tools such as ANSYS.
Maintain and leverage relationships with OSATs, substrate suppliers, and ecosystem partners to accelerate development.
Create and review mechanical drawings, stack‑ups, and layout constraints.
Lead failure analysis and root cause investigations for packaging and reliability issues.
Contribute to the packaging roadmap and scalability plan for automotive volume production.
Key Qualifications
10+ years of experience in IC packaging design and development, including leadership responsibilities.
Proven track record with multi‑chip packages, digital + RF integration, and automotive applications.
Deep knowledge of UCIe interconnects, interposers, and advanced packaging architectures.
Experience with RF antenna integration in package designs.
Proficient in Flip‑Chip, Fan‑Out, 2.5D integration, and heterogeneous system‑in‑package solutions.
Strong understanding of signal integrity, mechanical stress, thermal management, and reliability analysis.
Established network with packaging vendors and OSATs.
M.S. or Ph.D. in Mechanical Engineering, Materials Science, Electrical Engineering, or related field.
Excellent communication skills and ability to thrive in a fast‑paced start‑up environment.
Seniority level
Mid‑Senior level
Employment type
Full‑time
Job function
Engineering, Research, and Manufacturing
Industries
Semiconductor Manufacturing
Computer Hardware Manufacturing
Motor Vehicle Manufacturing
Referrals increase your chances of interviewing at Vivid Technology by 2x
Get notified about new Packaging Engineer jobs in San Jose, CA.
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Get AI-powered advice on this job and more exclusive features.
Direct message the job poster from Vivid Technology
This well-funded (Series B) start-up is building a new class of high-resolution perception sensing technology for ADAS and autonomous driving.
Seeking an IC Packaging Engineer to lead the development and delivery of advanced multi-chip packaging solutions for THz-system RFIC, SoC, and high-speed digital applications. This high-impact role combines technical leadership, hands‑on package design, and collaboration with OSATs, with a focus on 2.5D and interposer‑based architectures. The ideal candidate will have deep expertise in package physical design (layout, stack‑ups, DFM, SI/PI), thermal‑mechanical modelling, and high‑volume manufacturing and test, enabling them to execute designs directly or guide junior engineers toward production‑ready solutions.
Responsibilities
Technical leadership, guiding the design and execution of advanced IC packages for multi‑chip RFIC/SoC integration.
Develop 2.5D packages with UCIe chip‑to‑chip interconnects and interposer‑based solutions.
Work on single‑sided and double‑sided RDL designs and on‑package RF antenna structures.
Co‑optimize package designs for signal integrity, thermal, and mechanical performance in collaboration with RFIC, digital, and system engineers.
Drive material selection, DFM, and reliability qualification to meet automotive‑grade requirements (AEC‑Q).
Perform stress, warpage, and thermal simulations using tools such as ANSYS.
Maintain and leverage relationships with OSATs, substrate suppliers, and ecosystem partners to accelerate development.
Create and review mechanical drawings, stack‑ups, and layout constraints.
Lead failure analysis and root cause investigations for packaging and reliability issues.
Contribute to the packaging roadmap and scalability plan for automotive volume production.
Key Qualifications
10+ years of experience in IC packaging design and development, including leadership responsibilities.
Proven track record with multi‑chip packages, digital + RF integration, and automotive applications.
Deep knowledge of UCIe interconnects, interposers, and advanced packaging architectures.
Experience with RF antenna integration in package designs.
Proficient in Flip‑Chip, Fan‑Out, 2.5D integration, and heterogeneous system‑in‑package solutions.
Strong understanding of signal integrity, mechanical stress, thermal management, and reliability analysis.
Established network with packaging vendors and OSATs.
M.S. or Ph.D. in Mechanical Engineering, Materials Science, Electrical Engineering, or related field.
Excellent communication skills and ability to thrive in a fast‑paced start‑up environment.
Seniority level
Mid‑Senior level
Employment type
Full‑time
Job function
Engineering, Research, and Manufacturing
Industries
Semiconductor Manufacturing
Computer Hardware Manufacturing
Motor Vehicle Manufacturing
Referrals increase your chances of interviewing at Vivid Technology by 2x
Get notified about new Packaging Engineer jobs in San Jose, CA.
#J-18808-Ljbffr