Technical-Link N. America
Field-Programmable Gate Arrays Engineer
Technical-Link N. America, El Segundo, California, United States, 90245
Job Description
Technical-Link N. America provided pay range: Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.
Base pay range $100.00/hr - $130.00/hr
Professional Requirements
BSEE or BSCS, or equivalent; MSEE preferred
Candidate must be a U.S. citizen and able to qualify for DoD security clearance
10+ years of experience in a design engineering role focusing on functional verification
10+ years of ASIC/FPGA verification experience using SystemVerilog / UVM
Must have experience in: Developing verification plans, designing and implementing SystemVerilog / UVM test benches for constrained-random verification, developing functional coverage models, writing and debugging directed and random test cases, enabling test benches for hardware acceleration
Experience with automation/scripting (Perl, sed, awk, tcl/tk, sh)
C programming desirable; SystemC and C++ used in conjunction with chip design and verification highly desired
Experience with Formal verification / property checking is a plus
Experience with emulation or FPGA prototyping is a plus
RTL design experience and knowledge of standard protocols (such as PCIe) is a plus
FPGA experience is a plus
Seniority level
Mid‑Senior level
Employment type
Contract
Job function
Semiconductor Manufacturing
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Base pay range $100.00/hr - $130.00/hr
Professional Requirements
BSEE or BSCS, or equivalent; MSEE preferred
Candidate must be a U.S. citizen and able to qualify for DoD security clearance
10+ years of experience in a design engineering role focusing on functional verification
10+ years of ASIC/FPGA verification experience using SystemVerilog / UVM
Must have experience in: Developing verification plans, designing and implementing SystemVerilog / UVM test benches for constrained-random verification, developing functional coverage models, writing and debugging directed and random test cases, enabling test benches for hardware acceleration
Experience with automation/scripting (Perl, sed, awk, tcl/tk, sh)
C programming desirable; SystemC and C++ used in conjunction with chip design and verification highly desired
Experience with Formal verification / property checking is a plus
Experience with emulation or FPGA prototyping is a plus
RTL design experience and knowledge of standard protocols (such as PCIe) is a plus
FPGA experience is a plus
Seniority level
Mid‑Senior level
Employment type
Contract
Job function
Semiconductor Manufacturing
#J-18808-Ljbffr