Expedite Talent Solutions
US_East | Electrical / Electronics & Semiconductors Engineer_L3
Expedite Talent Solutions, Santa Clara, California, us, 95053
US_East | Electrical / Electronics & Semiconductors Engineer_L3
2 days ago – Be among the first 25 applicants
Possible 3 Month CTH | No Fees | Do Not Re-Post | Confidential
TMR ID: JWTN3L
Role: AMS CAD/Analog Engineer
Work location: Santa Clara, CA
Background and Meet and Greet: MANDATORY
Job Description
Bachelor's or master’s degree with 4+ years of CAD engineering experience
Experience in scripting languages such as Python
Proficient in using industry‑standard design software, including Cadence Virtuoso, Cadence/Calibre DRC, LVS tools
Experience supporting design teams working with analog and digital design flows
Excellent communication skills and ability to work with remote teams
Excellent programming skills in languages: SKILL, Perl; Python is a plus
Strong fundamentals in software development
Solid experience with EMIR (RV), Physical design verification (DRC/LVS/PEX/ERC), waiver
Key Responsibilities
Administer CAD EDA environment for analog and digital design teams
Support design flows from EDA vendors like Cadence, Synopsys, Mentor, Keysight, Ansys, and others
Write scripts to support design teams and flows using Python
Oversee physical verification tools and decks (DRC, LVS, Extraction, EM/IR, ESD, etc.), making custom modifications as needed
Develop and maintain infrastructure for custom PDK development (custom pcells, models, DRC, LVS, etc.)
Install and track foundry PDKs, including creating automated regression testing
Assist the infrastructure team in ensuring the availability and performance of computing resources
Mandatory Skills
Cadence / Synopsys / Mentor Analog layout tools (Preference: 5)
Python (Preference: 3)
Keysight / Ansys tools (Preference: 5)
#J-18808-Ljbffr
Possible 3 Month CTH | No Fees | Do Not Re-Post | Confidential
TMR ID: JWTN3L
Role: AMS CAD/Analog Engineer
Work location: Santa Clara, CA
Background and Meet and Greet: MANDATORY
Job Description
Bachelor's or master’s degree with 4+ years of CAD engineering experience
Experience in scripting languages such as Python
Proficient in using industry‑standard design software, including Cadence Virtuoso, Cadence/Calibre DRC, LVS tools
Experience supporting design teams working with analog and digital design flows
Excellent communication skills and ability to work with remote teams
Excellent programming skills in languages: SKILL, Perl; Python is a plus
Strong fundamentals in software development
Solid experience with EMIR (RV), Physical design verification (DRC/LVS/PEX/ERC), waiver
Key Responsibilities
Administer CAD EDA environment for analog and digital design teams
Support design flows from EDA vendors like Cadence, Synopsys, Mentor, Keysight, Ansys, and others
Write scripts to support design teams and flows using Python
Oversee physical verification tools and decks (DRC, LVS, Extraction, EM/IR, ESD, etc.), making custom modifications as needed
Develop and maintain infrastructure for custom PDK development (custom pcells, models, DRC, LVS, etc.)
Install and track foundry PDKs, including creating automated regression testing
Assist the infrastructure team in ensuring the availability and performance of computing resources
Mandatory Skills
Cadence / Synopsys / Mentor Analog layout tools (Preference: 5)
Python (Preference: 3)
Keysight / Ansys tools (Preference: 5)
#J-18808-Ljbffr