Google
SoC Physical Design Engineer
Join to apply for the
SoC Physical Design Engineer
role at
Google
About The Job In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems.
As a System on a Chip (SoC) Physical Design Engineer, you will collaborate with Register‑Transfer Level (RTL), Design for Testing (DFT), Floorplan, and full‑chip Sign off teams. Additionally, you will solve technical problems with innovative micro‑architecture and practical logic circuit solutions, while evaluating design options with optimized performance, power, and area in mind.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
The US base salary range for this full‑time position is $132,000‑$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Minimum qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with physical design.
Experience in physical design areas such as synthesis, place and route, Static Timing Analysis (STA), verification, or power analysis.
Preferred qualifications
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience in block/subchip level PnR for complex SoC.
Experience with multiple‑cycles of SoC in ASIC design.
Experience with scripting languages such as Perl, Python, or Tcl.
Experience with layout verification and design rules.
Experience in IP integration (e.g., memories, IO’s and Analog IP) with the knowledge of semiconductor device physics and transistor characteristics.
Responsibilities
Participate in the Physical Design of blocks for complex Tensor Processing Unit (TPU) chips.
Contribute to the design and closure of the subchip and individual blocks from Register‑Transfer Level‑to‑Graphic Design System.
Collaborate with RTL/Design and Product Development teams to achieve the best Power‑Performance‑Area (PPA) possible. This includes conducting feasibility studies for new micro‑architectures as well as optimizing runs for best Quality of Results (QoR).
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
#J-18808-Ljbffr
SoC Physical Design Engineer
role at
About The Job In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems.
As a System on a Chip (SoC) Physical Design Engineer, you will collaborate with Register‑Transfer Level (RTL), Design for Testing (DFT), Floorplan, and full‑chip Sign off teams. Additionally, you will solve technical problems with innovative micro‑architecture and practical logic circuit solutions, while evaluating design options with optimized performance, power, and area in mind.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
The US base salary range for this full‑time position is $132,000‑$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Minimum qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with physical design.
Experience in physical design areas such as synthesis, place and route, Static Timing Analysis (STA), verification, or power analysis.
Preferred qualifications
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience in block/subchip level PnR for complex SoC.
Experience with multiple‑cycles of SoC in ASIC design.
Experience with scripting languages such as Perl, Python, or Tcl.
Experience with layout verification and design rules.
Experience in IP integration (e.g., memories, IO’s and Analog IP) with the knowledge of semiconductor device physics and transistor characteristics.
Responsibilities
Participate in the Physical Design of blocks for complex Tensor Processing Unit (TPU) chips.
Contribute to the design and closure of the subchip and individual blocks from Register‑Transfer Level‑to‑Graphic Design System.
Collaborate with RTL/Design and Product Development teams to achieve the best Power‑Performance‑Area (PPA) possible. This includes conducting feasibility studies for new micro‑architectures as well as optimizing runs for best Quality of Results (QoR).
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
#J-18808-Ljbffr