Programmers.io
Analog Layout Engineer (Cupertino)
Programmers.io, Cupertino, California, United States, 95014
Hi
Hope you are doing well !
This is Dipendra Gupta from Programmers.ai as we have an urgent open role below, please check and do let me know if you are comfortable with Job description and looking for a new role or interested.
Analog Layout Engineer Cupertino CA Contract OR Fulltime
Required Skills: Knowledge of analog/mixed-signal IP (e.g., SERDES PHY, transmitter and receiver, PLL, DDR PHY, ADCs, DACs, LDOs, etc.) Experienced working with the circuit designer or layout lead to plan/schedule work and negotiate any layout trade-os as needed Reviewing and analyzing floor-plans and complex circuits with circuit designers Running complete set of design verification tools available Great understanding and experience using advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements Experienced in crafting well-matched, low noise, and low power analog blocks consisting of transistors, resistors, capacitors, pad IO's, ESD structures, etc. Must understand issues of IR drop, RC delay, electro-migration, self-heating and coupling capacitance Must recognize failure prone circuit and layout structures, have experience with analog and DFM standard methodologies, and enthusiastically work with circuit designer or layout lead for the best approach to problems High level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc., reports Knowledge of CADENCE Virtuoso and MENTOR GRAPHICS layout tools Best Regards, Dipendra Gupta Technical Recruiter Dipendra.gupta@programmers.ai
Hope you are doing well !
This is Dipendra Gupta from Programmers.ai as we have an urgent open role below, please check and do let me know if you are comfortable with Job description and looking for a new role or interested.
Analog Layout Engineer Cupertino CA Contract OR Fulltime
Required Skills: Knowledge of analog/mixed-signal IP (e.g., SERDES PHY, transmitter and receiver, PLL, DDR PHY, ADCs, DACs, LDOs, etc.) Experienced working with the circuit designer or layout lead to plan/schedule work and negotiate any layout trade-os as needed Reviewing and analyzing floor-plans and complex circuits with circuit designers Running complete set of design verification tools available Great understanding and experience using advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements Experienced in crafting well-matched, low noise, and low power analog blocks consisting of transistors, resistors, capacitors, pad IO's, ESD structures, etc. Must understand issues of IR drop, RC delay, electro-migration, self-heating and coupling capacitance Must recognize failure prone circuit and layout structures, have experience with analog and DFM standard methodologies, and enthusiastically work with circuit designer or layout lead for the best approach to problems High level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc., reports Knowledge of CADENCE Virtuoso and MENTOR GRAPHICS layout tools Best Regards, Dipendra Gupta Technical Recruiter Dipendra.gupta@programmers.ai