Samsung Semiconductor
Lead Performance Architect (Principal Engineer)
Samsung Semiconductor, Austin, Texas, us, 78716
Lead Performance Architect (Principal Engineer)
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Lead Performance Architect (Principal Engineer)
role at
Samsung Semiconductor
Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high‑performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!
Role And Responsibilities We’re seeking a Lead Performance Architect to join our System IP team where you will play a critical role in designing and optimizing the performance of our System IP, balancing requirements from key system components including CPU, GPU, and other IP blocks. You will be responsible for developing and maintaining performance models, analyzing system performance, and identifying optimization opportunities to improve overall system efficiency. Your expertise in performance modeling, analysis, and C++ coding will be essential in driving the development of high‑performance System IP solutions. Specialized experience working on memory subsystem, including interconnect, last‑level cache, coherency, and memory controller is a big plus.
Develop cycle‑accurate C++ performance models for System IP components, leading a team and contributing hands‑on.
Analyze system performance using various metrics such as latency, throughput, and power consumption to identify bottlenecks and optimization opportunities.
Develop and maintain performance analysis tools.
Collaborate with cross‑functional teams, including architecture, design, and software teams, to identify and implement performance optimization opportunities.
Run benchmarks to characterize system performance and identify areas for improvement.
Provide technical guidance and mentorship to junior engineers and contribute to best practices and standards for performance modeling and analysis.
Work closely with CPU, GPU, and SoC architecture teams to ensure that System IP components meet performance and power requirements.
Skills And Qualifications Minimum Requirements
20+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 18+ years with a Master’s Degree, or 16+ years with a PhD.
Expertise in performance modeling, analysis, and optimization, focused on System IP components.
Strong C++ coding skills, with experience developing cycle‑accurate performance models.
Strong understanding of computer architecture, microarchitecture, and system‑level performance optimization.
Excellent analytical and problem‑solving skills.
Strong technical leadership and mentoring skills.
Must be local, or open to relocating, to Austin, TX.
Nice to Have
Professional experience in memory subsystem or interconnect, with knowledge of memory hierarchy, access patterns, bandwidth, and latency optimization.
Proficiency in performance modeling tools such as SystemC, Gem5, or similar.
Experience with industry‑standard RTL design tools and methodologies.
Programming skills in Python or R, with data analysis, visualization, and automation experience.
Familiarity with emerging technologies, such as AI, ML, and autonomous systems, and their impact on System IP performance.
Our Team Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high‑volume products. We influence the product roadmap for a market‑leading system IP solution, focusing on delivering system modeling capability based on optimization and use‑case‑driven analysis (gaming, computational photography). Our performance‑ and power‑optimized IP solution is integrated into complex semiconductor products, aiming to reach multiple market segments. Joining a new team of talented individuals with diverse backgrounds, you will have limitless room to innovate and expand responsibilities, learning while shaping the team’s culture.
Total Rewards At Samsung – SARC/ACL, base pay ranges from $221,700 to $332,500, determined by education, skills, experience, and location. This exempt position is not eligible for overtime pay under the FLSA. Benefits include medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and more. The role may also be eligible for a long‑term incentive plan and relocation.
U.S. Export Control This position requires access to information subject to U.S. export control restrictions. Applicants must have or be eligible for government authorization.
Trade Secrets By submitting an application, the applicant agrees not to disclose or induce disclosure of Samsung’s confidential or proprietary information.
EEO Statement Samsung Electronics America, Inc. and its subsidiaries are committed to a diverse workforce and provide equal employment opportunity for all individuals regardless of protected characteristics.
Seniority level Mid‑Senior level
Employment type Full‑time
Job function Engineering and Information Technology
Industries Computers and Electronics Manufacturing
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Lead Performance Architect (Principal Engineer)
role at
Samsung Semiconductor
Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high‑performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!
Role And Responsibilities We’re seeking a Lead Performance Architect to join our System IP team where you will play a critical role in designing and optimizing the performance of our System IP, balancing requirements from key system components including CPU, GPU, and other IP blocks. You will be responsible for developing and maintaining performance models, analyzing system performance, and identifying optimization opportunities to improve overall system efficiency. Your expertise in performance modeling, analysis, and C++ coding will be essential in driving the development of high‑performance System IP solutions. Specialized experience working on memory subsystem, including interconnect, last‑level cache, coherency, and memory controller is a big plus.
Develop cycle‑accurate C++ performance models for System IP components, leading a team and contributing hands‑on.
Analyze system performance using various metrics such as latency, throughput, and power consumption to identify bottlenecks and optimization opportunities.
Develop and maintain performance analysis tools.
Collaborate with cross‑functional teams, including architecture, design, and software teams, to identify and implement performance optimization opportunities.
Run benchmarks to characterize system performance and identify areas for improvement.
Provide technical guidance and mentorship to junior engineers and contribute to best practices and standards for performance modeling and analysis.
Work closely with CPU, GPU, and SoC architecture teams to ensure that System IP components meet performance and power requirements.
Skills And Qualifications Minimum Requirements
20+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 18+ years with a Master’s Degree, or 16+ years with a PhD.
Expertise in performance modeling, analysis, and optimization, focused on System IP components.
Strong C++ coding skills, with experience developing cycle‑accurate performance models.
Strong understanding of computer architecture, microarchitecture, and system‑level performance optimization.
Excellent analytical and problem‑solving skills.
Strong technical leadership and mentoring skills.
Must be local, or open to relocating, to Austin, TX.
Nice to Have
Professional experience in memory subsystem or interconnect, with knowledge of memory hierarchy, access patterns, bandwidth, and latency optimization.
Proficiency in performance modeling tools such as SystemC, Gem5, or similar.
Experience with industry‑standard RTL design tools and methodologies.
Programming skills in Python or R, with data analysis, visualization, and automation experience.
Familiarity with emerging technologies, such as AI, ML, and autonomous systems, and their impact on System IP performance.
Our Team Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high‑volume products. We influence the product roadmap for a market‑leading system IP solution, focusing on delivering system modeling capability based on optimization and use‑case‑driven analysis (gaming, computational photography). Our performance‑ and power‑optimized IP solution is integrated into complex semiconductor products, aiming to reach multiple market segments. Joining a new team of talented individuals with diverse backgrounds, you will have limitless room to innovate and expand responsibilities, learning while shaping the team’s culture.
Total Rewards At Samsung – SARC/ACL, base pay ranges from $221,700 to $332,500, determined by education, skills, experience, and location. This exempt position is not eligible for overtime pay under the FLSA. Benefits include medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and more. The role may also be eligible for a long‑term incentive plan and relocation.
U.S. Export Control This position requires access to information subject to U.S. export control restrictions. Applicants must have or be eligible for government authorization.
Trade Secrets By submitting an application, the applicant agrees not to disclose or induce disclosure of Samsung’s confidential or proprietary information.
EEO Statement Samsung Electronics America, Inc. and its subsidiaries are committed to a diverse workforce and provide equal employment opportunity for all individuals regardless of protected characteristics.
Seniority level Mid‑Senior level
Employment type Full‑time
Job function Engineering and Information Technology
Industries Computers and Electronics Manufacturing
#J-18808-Ljbffr