Analog Devices is hiring: Embedded Adaptive Hardware Engineer in San Jose

Get AI-powered advice on this job and more exclusive features. Overview Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. What you’ll be doing The group is seeking an experienced Embedded Adaptive Hardware Designer to contribute to the development of the eFPGA architecture and softlogic IDE. You do NOT need to be an eFPGA expert yet need to be experienced in digital hardware/architecture design. The job responsibilities include: Document eFPGA architecture, specifications, user guides, and design process. Upgrade eFPGA architecture and RTL for advanced features such as functional safety and ASIL‑D automotive qualification. Perform hardware‑software co‑design, such as PPA analysis/optimization and the debug environment. Develop the softlogic library (library of RTLs that will be programmed into the eFPGA) as part of the developer‑friendly IDE that will be integrated into ADI’s CodeFusion Studio. Port eFPGA hardware IP to advanced technology nodes such as TSMC 16FFC, TSMC N4/N5. Integrate eFPGA IP into the chip with the SoC design team. Interact with the eFPGA verification and PnR team for design iteration. Qualifications Master’s degree (or equivalent experience) in Electrical Engineering or related field. Knowledge of system‑level protocols and operations (e.g., AHB, AXI). Basic understanding of design verification. Deeply inquisitive and able to use core technical competencies to provide direction on system architecture. Excellent communication skills to work well with multi‑functional teams (SoC integration, physical‑design, software, marketing, etc.). Strong EE fundamentals, knowledgeable in computer architecture, timing analysis, process variations, statistical error rates, and power analysis. Ways to stand out from the crowd 5+ years of proven experience in SoC/microarchitecture design and RTL coding. Tapeout experience in advanced nodes (N4/N5 or similar). Understanding of functional‑safety (FuSA) hardware requirements. Understanding of chiplet protocols (e.g., UCIe) and characterization/validation methods in the post‑silicon environment. Benefits & Compensation The expected wage range for a new hire into this position is $144,038 to $216,056. Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors. This position qualifies for a discretionary performance‑based bonus based on personal and company factors. Benefits include medical, vision, and dental coverage, 401(k), paid vacation, holidays, and sick time. Travel & Employment Details Required Travel: Yes (10% of the time). Shift Type: 1st Shift/Days. Employment Type: Full‑time. Seniority Level: Mid‑Senior level. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. EEO is the Law: Notice of Applicant Rights Under the Law. #J-18808-Ljbffr