Senior ASIC Verification Engineer — Cybersecurity & Networking Job at Palo Alto

A leading cybersecurity company based in California seeks a Design Verification Engineer to join their ASIC team. The successful candidate will ensure that ASICs meet industry-leading requirements for performance and reliability. Responsibilities include collaborating on verification plans, developing methodologies, and automating verification tasks. Candidates should possess over 5 years of experience in ASIC verification and expertise in SystemVerilog and UVM. A competitive salary between $235,000 – $260,000 is offered, along with benefits. #J-18808-Ljbffr