Renesas Electronics Corporation
Job Description
Our team guarantees Gate netlist and SDC (Synopsys Design Constraint) qualification for Automotive SoCs. Our responsibilities include :
RTL/Netlist qualification
Perform LSI ChipTop netlist checks such as VC Spyglass CDC, Renesas In-House Tool such as FalseCheck for asynchronous design
Monitor and control error judgment progress
SDC management for each milestone
Hierarchical SDC creation
IP level constraint integration
Deliver high-quality SDC data to other design teams
Support debugging for project members
Monitor and control GCA (Galaxy constraint analysis), PTE (PrimeTime error), Tempus Error/Warning judgment progress
ECO timing
Collaborate with other design teams (DFT, ME/STA, BE/Layout) to develop schedules and solve timing closure issues until TapeOut
Qualifications
Masters or Bachelor degree in Electrical or Computer Engineering Proficiency in circuit/schematic analysis for SDC debugging and asynchronous design Experience with STA (Static Timing Analysis) Good communication and problem-solving skills Ability to work under pressure and multitask Experience with Cadence tools (Tempus), Synopsys tools (VC Spyglass CDC, PrimeTime, RTLA) Experience with scripting languages such as C-Shell, Python, Perl, Tcl, Visual Basic Proficiency in MS Office tools, especially Excel Additional Information
Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As an industry leader in embedded processing, we offer scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries, backed by a broad product portfolio including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With over 21,000 professionals across more than 30 countries, we continue to expand our boundaries to provide innovative, sustainable, and power-efficient solutions that enhance user experiences and support communities worldwide. Our culture emphasizes career growth, impact, and wellbeing, offering flexible and inclusive work environments, remote options, and Employee Resource Groups. If you're ready to own your success and make your mark, join Renesas. Let’s
Shape the Future
together. Renesas Electronics is an equal opportunity employer committed to diversity and inclusion. For more information, read our
Diversity & Inclusion Statement .
#J-18808-Ljbffr
Masters or Bachelor degree in Electrical or Computer Engineering Proficiency in circuit/schematic analysis for SDC debugging and asynchronous design Experience with STA (Static Timing Analysis) Good communication and problem-solving skills Ability to work under pressure and multitask Experience with Cadence tools (Tempus), Synopsys tools (VC Spyglass CDC, PrimeTime, RTLA) Experience with scripting languages such as C-Shell, Python, Perl, Tcl, Visual Basic Proficiency in MS Office tools, especially Excel Additional Information
Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As an industry leader in embedded processing, we offer scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries, backed by a broad product portfolio including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With over 21,000 professionals across more than 30 countries, we continue to expand our boundaries to provide innovative, sustainable, and power-efficient solutions that enhance user experiences and support communities worldwide. Our culture emphasizes career growth, impact, and wellbeing, offering flexible and inclusive work environments, remote options, and Employee Resource Groups. If you're ready to own your success and make your mark, join Renesas. Let’s
Shape the Future
together. Renesas Electronics is an equal opportunity employer committed to diversity and inclusion. For more information, read our
Diversity & Inclusion Statement .
#J-18808-Ljbffr