Memory Subsystem Verification Engineer (UVM/SystemVerilog)

A leading semiconductor company is seeking a Verification Engineer in Austin, TX to design and implement advanced verification environments for memory subsystems. The ideal candidate will have strong proficiency in C/C++, System Verilog, and UVM, with experience in IP verification. Complex tasks include developing test benches and collaborating with teams for comprehensive verification processes. This role offers a dynamic work environment and is essential in shaping the future of advanced memory solutions. #J-18808-Ljbffr