Analog Layout Lead: High‑Speed SerDes & Mixed‑Signal

A semiconductor design firm is seeking an Analog Layout Design Lead to oversee the implementation of high-performance analog and mixed-signal IP. The role requires 10–20 years of experience in custom layout, with a strong focus on High-Speed SerDes layouts and FinFET nodes. As a hands-on technical leader, you will mentor engineers and define layout methodologies while collaborating with circuit design and verification teams. Competitive full-time position based in California. #J-18808-Ljbffr