BCforward
Silicon Physical Design Engineer III
BCforward is seeking a Physical Design Engineer III to work remote
Start/End Dates: 1/19/2026 – 1/18/2027
Location: US – CA Remote
Job Title: Hardware Engineering – Silicon Physical Design Engineer III
Strong understanding in the RTL2GDSII flow and design tapeouts in 16nm/14nm or below process technologies
Experience with low power implementation, power gating, multiple voltage rails, strong UPF/CPF knowledge.
Experience working with most EDA tools like DC/Genus, ICC2/Innovus, Primetime, PTPX, Primepower
Duties
Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.
Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
Power analysis based on netlist
Skills Must Have
5 years of relevant physical design experience
Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs
Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
Experience in chip power analysis
Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques.
Experience with Python, TCL, Perl programming
Wish List/ Nice to Have
MSEE/CS or equivalent experience
Education Must Have
Bachelor degree in Electrical/Computer Engineering or Computer Science
Master’s Degree preferred but not required
Pursuant to the California Fair Chance Act, Los Angeles County Fair Chance Ordinance for Employers, Los Angeles Fair Chance Initiative for Hiring Ordinance, and San Francisco Fair Chance Ordinance, qualified applicants will be considered for assignment with arrest and conviction records. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness, meet client expectations, standards, and accompanying requirements, and safeguard business operations and company reputation.
Interested candidates please send resume in Word format Please reference job code 248139 when responding to this ad.
#J-18808-Ljbffr
Strong understanding in the RTL2GDSII flow and design tapeouts in 16nm/14nm or below process technologies
Experience with low power implementation, power gating, multiple voltage rails, strong UPF/CPF knowledge.
Experience working with most EDA tools like DC/Genus, ICC2/Innovus, Primetime, PTPX, Primepower
Duties
Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.
Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
Power analysis based on netlist
Skills Must Have
5 years of relevant physical design experience
Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs
Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
Experience in chip power analysis
Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques.
Experience with Python, TCL, Perl programming
Wish List/ Nice to Have
MSEE/CS or equivalent experience
Education Must Have
Bachelor degree in Electrical/Computer Engineering or Computer Science
Master’s Degree preferred but not required
Pursuant to the California Fair Chance Act, Los Angeles County Fair Chance Ordinance for Employers, Los Angeles Fair Chance Initiative for Hiring Ordinance, and San Francisco Fair Chance Ordinance, qualified applicants will be considered for assignment with arrest and conviction records. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness, meet client expectations, standards, and accompanying requirements, and safeguard business operations and company reputation.
Interested candidates please send resume in Word format Please reference job code 248139 when responding to this ad.
#J-18808-Ljbffr