Chelsea Search Group
Senior Design Verification Engineer (remote)
Chelsea Search Group, San Diego, California, United States, 92189
Senior Design Verification Engineer
Remote / work from home
US Citizen or US Permanent Resident
Full-time/employee + Benefits + 401k + Stock Options
Responsibilities:
Develop and execute verification plans for digital designs using SystemVerilog and UVM Create and maintain testbenches, test cases, and test vectors Contribute to the development of novel methodologies and verification techniques Run simulations to verify design against specifications and analyze results, identify issues, and debug designs Implement coverage tracking and metrics Document plans, environments, test cases, and all results for a comprehensive record of all verification strategies Your primary responsibilities will include developing test plans, writing testbenches and tests, and debugging any bugs found with the RTL team.
Required Skills:
BSEE/MSEE with 5+ years of hands-on experience in SoC verification using UVM Experience in gate level simulation setup and process corner failure analysis Experience using Synopsys verification tools such as VCS, Verdi, and Spyglass Experience with digital design concepts and ASIC development flow Experience writing and debugging RTL using SystemVerilog Programming experience using C, C++, and/or Python/Perl Ability to work collaboratively across teams and communicate effectively Ability to multi-task and prioritize in a fast-paced environment; managing multiple complex, multidisciplinary tasks and projects
Preferred Skills:
Experience verifying high-speed interfaces such as PCIe and DDR Experience verifying RISC-V based systems Experience with emulation or FPGA prototyping Experience with formal verification methodologies Experience with the Chisel hardware description language Experience with version control systems (e.g., Git) and Continuous Integration/Continuous Deployment (CI/CD) pipelines
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Responsibilities:
Develop and execute verification plans for digital designs using SystemVerilog and UVM Create and maintain testbenches, test cases, and test vectors Contribute to the development of novel methodologies and verification techniques Run simulations to verify design against specifications and analyze results, identify issues, and debug designs Implement coverage tracking and metrics Document plans, environments, test cases, and all results for a comprehensive record of all verification strategies Your primary responsibilities will include developing test plans, writing testbenches and tests, and debugging any bugs found with the RTL team.
Required Skills:
BSEE/MSEE with 5+ years of hands-on experience in SoC verification using UVM Experience in gate level simulation setup and process corner failure analysis Experience using Synopsys verification tools such as VCS, Verdi, and Spyglass Experience with digital design concepts and ASIC development flow Experience writing and debugging RTL using SystemVerilog Programming experience using C, C++, and/or Python/Perl Ability to work collaboratively across teams and communicate effectively Ability to multi-task and prioritize in a fast-paced environment; managing multiple complex, multidisciplinary tasks and projects
Preferred Skills:
Experience verifying high-speed interfaces such as PCIe and DDR Experience verifying RISC-V based systems Experience with emulation or FPGA prototyping Experience with formal verification methodologies Experience with the Chisel hardware description language Experience with version control systems (e.g., Git) and Continuous Integration/Continuous Deployment (CI/CD) pipelines
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