Senior ASIC Verification Engineer - Hybrid, Equity Eligible

A leading technology company is looking for a Senior ASIC Design Verification Engineer in Santa Clara, CA. Responsibilities include developing innovative IPs and unit verification. Candidates should have strong skills in OOP, System Verilog, and VCS, along with a BSEE or equivalent experience. The position offers a competitive salary ranging from $136,000 to $264,500, with a commitment to diversity and equal opportunity. #J-18808-Ljbffr