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Broadcom

IC DESIGN ENGINEER

Broadcom, San Jose, California, United States, 95199

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IC DESIGN ENGINEER

– Broadcom

Job Description ASIC/Layout Design Engineer responsible for definition, design, verification, and documentation of ASICs. Duties include determining architecture, logic design, and system simulation, defining module interfaces for simulation, and contributing to multidimensional designs involving complex integrated circuits. Evaluates all aspects of the process flow from high‑level design to synthesis, place & run, timing, and power use. Analyzes equipment, conducts experimental tests, evaluates results, and may review vendor capabilities.

Knowledge:

Uses broad expertise or unique knowledge to achieve company objectives creatively and effectively.

Job Complexity:

Handles significant issues requiring evaluation of intangibles, exercises independent judgment, and creates formal networks across groups.

Supervision:

Determines methods on new assignments and may supervise others.

Responsibilities

Work as part of a physical design team implementing chips from netlist to GDSII with a good understanding of technology elements and all stages of design flow.

Responsible for floorplanning, design partition, and block pin assignment.

Perform block PnR, timing closure, and physical verification.

Conduct block IR/EM analysis; experience with chip‑level IR/EM analysis is a big plus.

Familiar with scripting languages such as TCL, Perl, and Python; write scripts to automate the physical design flow and improve efficiency.

Expertise on low‑power IC design is desirable.

Good knowledge of physical verification using Mentor’s Calibre tool.

Minimum Requirements Bachelor’s degree and 8+ years of related experience or Master’s degree with 5+ years of experience.

Compensation and Benefits The annual base salary range is $120,000 - $192,000.

The position is eligible for a discretionary annual bonus and equity.

Broadcom offers a competitive and comprehensive benefits package, including medical, dental and vision plans; 401(K) participation with company matching; Employee Stock Purchase Program (ESPP); Employee Assistance Program (EAP); company‑paid holidays; paid sick leave and vacation time; compliance with Paid Family Leave and other applicable leaves of absence.

Seniority Level Mid‑Senior level

Employment Type Full‑time

Job Function Engineering and Information Technology; Industries: Semiconductor Manufacturing.

R024617

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