Hewlett Packard Enterprise Company in
ASIC Test development Engineer
Hewlett Packard Enterprise Company in, San Jose, California, United States, 95199
ASIC Test Development Engineer (Finance)
Hybrid, average 2 days per week in an HPE office. Individual contributor role responsible for testability solutions of ASICs, memory, and 2.5D SiPs for Juniper's product development and manufacturing, including both structured ATE‑level and system‑level/mission‑mode environments.
Roles
Develop test strategy and DFT solutions for ASICs and 2.5D SiP supporting high test coverage requirements.
Concentrate on Pre‑P0 development and coordinate between hardware engineering and supplier development teams.
Work closely with design teams to enable DFT features, validate on ATE, integrate in diagnostics, and implement in manufacturing tests.
Develop innovative DFT IP in collaboration with cross‑functional teams inside and outside the company.
Work closely with component engineers to resolve high DPPM ASIC issues at EMS partner sites.
Engage in test standard working groups, such as IEEE 1149, 1687, P1838, JC‑42 Solid State Memories.
Provide trusted advisory on ASIC testability to Juniper teams—ASIC frontend, physical design, DFT, system software, diagnostics, hardware and manufacturing test teams—throughout the product lifecycle.
Advocate for and bridge structural vs functional test coverage gaps, applying new fault models for advanced semiconductor nodes.
Demonstrate innovation via patents, technical papers and conference presentations.
Own ASIC test requirements for ASIC MRDs, phase‑exit validation, advanced test mode development, fault coverage attainment, manufacturability objectives and continuous improvement.
Voice of test authority with ASIC suppliers, solving supplier issues (e.g., NTF) and influencing supplier testing to implement Juniper‑favorable manufacturability modes.
Qualifications
Demonstrated Principal or Distinguished Engineer expertise.
15+ years in testability and DFT for ASICs, memories, and 2.5D SiPs.
Expertise in state‑of‑the‑art DFT techniques: MBIST, IOBIST, LBIST, JTAG, scan/ATPG, and IEEE 1687.
Hands‑on experience implementing ASIC DFT, post‑silicon validation, debug and diagnostic integration.
Experience with high‑performance ASICs, TSV, HBM, 2.5D, and 3D IC test challenges and solutions.
Broad experience collaborating with ASIC suppliers, IP/EDA vendors, 2.5D SiP partners and contract manufacturers.
Excellent communication, collaboration and program‑management skills, able to influence others independently.
Education BS, MS or PhD Electrical Engineering.
Additional Skills
Accountability, Action Planning, Active Learning, Active Listening, Agile Methodology, Agile Scrum Development, Analytical Thinking, Bias, Coaching, Creativity, Critical Thinking, Cross‑Functional Teamwork, Data Analysis Management, Design, Design Thinking, Empathy, Follow‑Through, Group Problem Solving, Growth Mindset, Intellectual Curiosity, Long Term Planning, Managing Ambiguity.
Equal Employment Opportunity Statement Hewlett Packard Enterprise is an Equal Employment Opportunity/Veteran/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions are based on qualifications, merit and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together.
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Roles
Develop test strategy and DFT solutions for ASICs and 2.5D SiP supporting high test coverage requirements.
Concentrate on Pre‑P0 development and coordinate between hardware engineering and supplier development teams.
Work closely with design teams to enable DFT features, validate on ATE, integrate in diagnostics, and implement in manufacturing tests.
Develop innovative DFT IP in collaboration with cross‑functional teams inside and outside the company.
Work closely with component engineers to resolve high DPPM ASIC issues at EMS partner sites.
Engage in test standard working groups, such as IEEE 1149, 1687, P1838, JC‑42 Solid State Memories.
Provide trusted advisory on ASIC testability to Juniper teams—ASIC frontend, physical design, DFT, system software, diagnostics, hardware and manufacturing test teams—throughout the product lifecycle.
Advocate for and bridge structural vs functional test coverage gaps, applying new fault models for advanced semiconductor nodes.
Demonstrate innovation via patents, technical papers and conference presentations.
Own ASIC test requirements for ASIC MRDs, phase‑exit validation, advanced test mode development, fault coverage attainment, manufacturability objectives and continuous improvement.
Voice of test authority with ASIC suppliers, solving supplier issues (e.g., NTF) and influencing supplier testing to implement Juniper‑favorable manufacturability modes.
Qualifications
Demonstrated Principal or Distinguished Engineer expertise.
15+ years in testability and DFT for ASICs, memories, and 2.5D SiPs.
Expertise in state‑of‑the‑art DFT techniques: MBIST, IOBIST, LBIST, JTAG, scan/ATPG, and IEEE 1687.
Hands‑on experience implementing ASIC DFT, post‑silicon validation, debug and diagnostic integration.
Experience with high‑performance ASICs, TSV, HBM, 2.5D, and 3D IC test challenges and solutions.
Broad experience collaborating with ASIC suppliers, IP/EDA vendors, 2.5D SiP partners and contract manufacturers.
Excellent communication, collaboration and program‑management skills, able to influence others independently.
Education BS, MS or PhD Electrical Engineering.
Additional Skills
Accountability, Action Planning, Active Learning, Active Listening, Agile Methodology, Agile Scrum Development, Analytical Thinking, Bias, Coaching, Creativity, Critical Thinking, Cross‑Functional Teamwork, Data Analysis Management, Design, Design Thinking, Empathy, Follow‑Through, Group Problem Solving, Growth Mindset, Intellectual Curiosity, Long Term Planning, Managing Ambiguity.
Equal Employment Opportunity Statement Hewlett Packard Enterprise is an Equal Employment Opportunity/Veteran/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions are based on qualifications, merit and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together.
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