Tara Technical Solutions (TTS)
Design Verification Engineer
Tara Technical Solutions (TTS), San Francisco, California, United States, 94199
Tara Technical Solutions
Recruiting for a Principal ASIC Verification Engineer role. Principal ASIC Verification Engineer – San Jose
Full‑time, direct hire with a Fortune 500 client. Pay range: $140,000 – $225,000 per year (actual pay based on skills and experience). Qualifications
A Bachelor’s Degree in Electrical and Electronic Engineering, Computer Science, or equivalent. 12+ years of relevant industry work experience. Experience verifying designs at system level and block level. Fluent knowledge of RTL verification methodologies including SystemVerilog. Strong experience in ASIC design verification flows and DV methodologies. Strong working knowledge of object‑oriented verification languages (OVM, UVM, etc.), C/C++, Perl, and scripting skills. Strong and independent design debugging capability. Strong verbal and written communication skills; comfort working in a team environment. Demonstrated ability to analyze and resolve complex verification trade‑off scenarios. Legal authorization to work in the US. Experience with hardware design and debug, C++/SystemC and other programming languages. Experience with emulators and FPGA‑based prototyping. Familiarity with overall chip design methodologies and tools. Knowledge of CPU, DDR, Bus Protocol, Network Protocol, or DSP design preferred. Benefits
Medical insurance Vision insurance 401(k) Pension plan Child care support Paid maternity leave Paid paternity leave Student loan assistance Tuition assistance Disability insurance
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Recruiting for a Principal ASIC Verification Engineer role. Principal ASIC Verification Engineer – San Jose
Full‑time, direct hire with a Fortune 500 client. Pay range: $140,000 – $225,000 per year (actual pay based on skills and experience). Qualifications
A Bachelor’s Degree in Electrical and Electronic Engineering, Computer Science, or equivalent. 12+ years of relevant industry work experience. Experience verifying designs at system level and block level. Fluent knowledge of RTL verification methodologies including SystemVerilog. Strong experience in ASIC design verification flows and DV methodologies. Strong working knowledge of object‑oriented verification languages (OVM, UVM, etc.), C/C++, Perl, and scripting skills. Strong and independent design debugging capability. Strong verbal and written communication skills; comfort working in a team environment. Demonstrated ability to analyze and resolve complex verification trade‑off scenarios. Legal authorization to work in the US. Experience with hardware design and debug, C++/SystemC and other programming languages. Experience with emulators and FPGA‑based prototyping. Familiarity with overall chip design methodologies and tools. Knowledge of CPU, DDR, Bus Protocol, Network Protocol, or DSP design preferred. Benefits
Medical insurance Vision insurance 401(k) Pension plan Child care support Paid maternity leave Paid paternity leave Student loan assistance Tuition assistance Disability insurance
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