Cypress HCM
Sr. Analog Mixed-Signal Design Engineer
Cypress HCM, San Jose, California, United States, 95199
This range is provided by Cypress HCM. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.
Base pay range $115,000.00/yr - $208,000.00/yr
Additional compensation types Annual Bonus, Sign‑on bonus, and RSUs
Sr. Analog/Mixed‑Signal Design Engineer This exciting role will be responsible for circuit design and implementation at the chip or block level, developing high‑performance analog and mixed‑signal components such as transmitters, receivers, PLLs, DLLs, ADCs, and DACs. The role involves circuit simulation, layout collaboration, behavioral modeling, and silicon validation. They are headquartered in the San Jose, CA area, and this position can sit in either San Jose, CA, or Atlanta, GA area. The company is a silicon IP provider for the semiconductor manufacturing industry. If you are an individual who has expertise in designing complex high‑speed circuits and loves to be hands‑on, this role could be for you!
Responsibilities
Own and implement analog/mixed‑signal designs at the chip or block level to meet performance and timing goals.
Design, simulate, and characterize high‑speed circuits such as transmitters, receivers, PLLs, DLLs, ADCs, DACs, and LDOs.
Develop and validate circuit architectures, perform post‑layout verification, and document analysis results.
Collaborate with layout, lab, and system teams for silicon bring‑up, test planning, and characterization.
Create behavioral models for verification simulations and support pre‑silicon verification flows.
Qualifications
MS or PhD in Electrical Engineering with 2+ years of CMOS analog/mixed‑signal design experience.
Hands‑on experience in one or more circuits: transmitters, receivers (CTLE, DFE), PLLs, DLLs, or clock distribution.
Strong understanding of analog fundamentals, bias circuits, op‑amps, and design tradeoffs.
Experience with DDR4/5 or PCIe interface design preferred.
Familiarity with FinFET and digitally assisted design a plus.
Skilled in modeling with MATLAB, Verilog‑A, or Verilog.
Strong communication and teamwork abilities in a cross‑functional R&D environment.
Salary Range
$115,000-208,000+ depending on experience and location.
Weekly Schedule
Hybrid schedule (3 days onsite and 2 days remote), based in either San Jose, CA, or Johns Creek, GA.
Seniority level
Mid‑Senior level
Employment type
Full‑time
Job function
Quality Assurance, Engineering, and Manufacturing
Industries
Semiconductor Manufacturing, Computers and Electronics Manufacturing, and Appliances, Electrical, and Electronics Manufacturing
Benefits
Medical insurance
Vision insurance
401(k)
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Base pay range $115,000.00/yr - $208,000.00/yr
Additional compensation types Annual Bonus, Sign‑on bonus, and RSUs
Sr. Analog/Mixed‑Signal Design Engineer This exciting role will be responsible for circuit design and implementation at the chip or block level, developing high‑performance analog and mixed‑signal components such as transmitters, receivers, PLLs, DLLs, ADCs, and DACs. The role involves circuit simulation, layout collaboration, behavioral modeling, and silicon validation. They are headquartered in the San Jose, CA area, and this position can sit in either San Jose, CA, or Atlanta, GA area. The company is a silicon IP provider for the semiconductor manufacturing industry. If you are an individual who has expertise in designing complex high‑speed circuits and loves to be hands‑on, this role could be for you!
Responsibilities
Own and implement analog/mixed‑signal designs at the chip or block level to meet performance and timing goals.
Design, simulate, and characterize high‑speed circuits such as transmitters, receivers, PLLs, DLLs, ADCs, DACs, and LDOs.
Develop and validate circuit architectures, perform post‑layout verification, and document analysis results.
Collaborate with layout, lab, and system teams for silicon bring‑up, test planning, and characterization.
Create behavioral models for verification simulations and support pre‑silicon verification flows.
Qualifications
MS or PhD in Electrical Engineering with 2+ years of CMOS analog/mixed‑signal design experience.
Hands‑on experience in one or more circuits: transmitters, receivers (CTLE, DFE), PLLs, DLLs, or clock distribution.
Strong understanding of analog fundamentals, bias circuits, op‑amps, and design tradeoffs.
Experience with DDR4/5 or PCIe interface design preferred.
Familiarity with FinFET and digitally assisted design a plus.
Skilled in modeling with MATLAB, Verilog‑A, or Verilog.
Strong communication and teamwork abilities in a cross‑functional R&D environment.
Salary Range
$115,000-208,000+ depending on experience and location.
Weekly Schedule
Hybrid schedule (3 days onsite and 2 days remote), based in either San Jose, CA, or Johns Creek, GA.
Seniority level
Mid‑Senior level
Employment type
Full‑time
Job function
Quality Assurance, Engineering, and Manufacturing
Industries
Semiconductor Manufacturing, Computers and Electronics Manufacturing, and Appliances, Electrical, and Electronics Manufacturing
Benefits
Medical insurance
Vision insurance
401(k)
#J-18808-Ljbffr