Senior Software Engineer - Virtual Hardware Modeling Job at DATAMETRICS SOFTWARE

Senior Software Engineer - Virtual Hardware Modeling

Role: Senior Software Engineer - Virtual Hardware Modeling

Experience: 12+ years

Job Type: W2 Only

Must Skills:

• High proficiency in modern C++ in the domains of chip‑design, electronic design automation or simulation.
• Experience with the SystemC/TLM library.
• Experience with virtual platform development tools and frameworks, such as Synopsys Virtualizer, Cadence Virtual Platform, Imperas OVP, or ARM Fast Models.
• Familiarity with processor/DSP architectures, such as ARM, RISC‑V, and Xtensa.
• Familiarity with NoC, MMU, address translations, and cache modeling.
• Familiarity with the standard C++ concurrency support library: threads, atomic operations, memory ordering, etc.
• Proficiency in Python to automate design flows and create collateral data.

Key Responsibilities:

• Design and develop SystemC TLM models to represent the SoC architecture, integrating emulated processors, DSPs, Network‑on‑Chip, DMA, and memory controllers.
• Integrate first‑party and vendor models into the Virtual Platform, developing automated workflows to ensure register‑level accuracy and complete connectivity at the SoC level, minimizing manual intervention and enabling continuous integration.
• Collaborate with silicon architects, digital designers, and verification engineers to create high‑fidelity, fast C++ models for first‑party IP.
• Coordinate virtual platforms with hardware development programs, validating multiple SoCs and architectural changes with system software and firmware engineering to enable end‑to‑end silicon validation test frameworks.
• Enhance virtual platforms to enable SoC and system architecture exploration by instrumenting models for power and performance metrics, allowing data‑driven design decisions and trade‑off analysis to optimize system performance and power consumption.

Qualifications:

• B.S. degree in Computer Science or Electrical Engineering or equivalent experience.
• 7‑10+ years of experience, including 5+ years in hardware model simulation, virtual platform, and performance modeling of complex SoCs or high‑fidelity hardware accelerators.
• High proficiency in modern C++ for chip‑design, electronic design automation or simulation.
• Experience with the SystemC/TLM library.
• Experience with virtual platform development tools and frameworks, such as Synopsys Virtualizer, Cadence Virtual Platform, Imperas OVP, or ARM Fast Models.
• Familiarity with processor/DSP architectures, such as ARM, RISC‑V, and Xtensa.
• Familiarity with NoC, MMU, address translations, and cache modeling.
• Familiarity with the standard C++ concurrency support library: threads, atomic operations, memory ordering, etc.
• Proficiency in Python to automate design flows and create collateral data.