Eliyan
Join the leading chiplet startup! As an Eliyan NuLink PHY IO Architect, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best‑class power, area, manufacturability, and design flexibility. You will drive the definition and development of cutting‑edge ASICs from RTL to GDSII. You will work with a cross‑functional team of industry experts that operate from first principles, innovate, and push the envelope to create high‑volume and high‑performance manufacturable products. In this role, you will own the architecture, oversee design and validation, and be a focal point for customer and marketing team interactions. You will also focus on developing and improving design flows and methodologies to ensure high‑quality, on‑time delivery. We offer a fun work environment with excellent benefits. ONSITE M‑F
Key Responsibilities
Architecture:
Define NuLink PHY subsystems (physical and logical/link layers) and hierarchical modular protocol bridges between PCIe, AXI4, APB, CHI, CXL (.io/.cache/.mem), DDR to name a few. Definition of a firmware first based hardware architecture approach.
Protocol Design:
Design protocol conversion layers with transaction ordering, credit‑based flow control, QoS, address translation, coherency management, and memory semantics across protocol domains
Performance Evaluation and Optimization:
Model and tune PHY data path, link protocols, and CDC architectures for protocol efficiency, bandwidth, latency, power, and signal integrity. Conduct technical evaluation and benchmark analysis against internal and external IPs.
Collaboration:
Partner with ASIC, firmware, and post‑silicon teams. Support customer integration for compute‑to‑memory (CXL/DDR), processor interconnect (AXI/PCIe), and control plane (APB). Create clear and comprehensive architecture specifications with foolproof integration guidelines.
Validation:
Review characterization plans for PLL, VCO, ATB, and link training. Create protocol testbenches validating transaction handling, latency, throughput, and compliance
Compliance:
Ensure UCIe, PCIe, CXL, AMBA AXI/APB, and DDR specification compliance. Define interoperability requirements and protocol error handling. Be part of industry standards bodies and work groups to keep Eliyan's product implementations up to date with the latest versions of the standards.
Leadership:
Mentor engineers on protocol implementation, timing constraints, and hierarchical design. Effectively collaborate with industry technologists, business leaders and ability to network seamlessly with industry peers to influence stakeholders.
Minimum Qualifications
Expertise in multiple areas of architecture definition, chip micro‑architecture, protocol definition and implementation
Strong knowledge of two or more of the following connectivity protocols - PCIe, UCIe, UALink, Ethernet, DDR, AMBA
Strong scripting and automation skills
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
8+ years’ of experience
Ideal Qualifications
15+ years of experience in ASIC architecture with strong bias for practical logic design and influence of physical implementation, with a proven track record of leading teams through successful tapeouts
Performance modeling of hardware implementations with high level languages like C, C++ or SystemC
Adept at clocking and floorplan guidelines for PHY implementation
Extremely knowledgeable on RTL-to-GDSII flows, limitations, and flexibilities to improve productivity and power aware designs
Exceptional problem‑solving skills.
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Key Responsibilities
Architecture:
Define NuLink PHY subsystems (physical and logical/link layers) and hierarchical modular protocol bridges between PCIe, AXI4, APB, CHI, CXL (.io/.cache/.mem), DDR to name a few. Definition of a firmware first based hardware architecture approach.
Protocol Design:
Design protocol conversion layers with transaction ordering, credit‑based flow control, QoS, address translation, coherency management, and memory semantics across protocol domains
Performance Evaluation and Optimization:
Model and tune PHY data path, link protocols, and CDC architectures for protocol efficiency, bandwidth, latency, power, and signal integrity. Conduct technical evaluation and benchmark analysis against internal and external IPs.
Collaboration:
Partner with ASIC, firmware, and post‑silicon teams. Support customer integration for compute‑to‑memory (CXL/DDR), processor interconnect (AXI/PCIe), and control plane (APB). Create clear and comprehensive architecture specifications with foolproof integration guidelines.
Validation:
Review characterization plans for PLL, VCO, ATB, and link training. Create protocol testbenches validating transaction handling, latency, throughput, and compliance
Compliance:
Ensure UCIe, PCIe, CXL, AMBA AXI/APB, and DDR specification compliance. Define interoperability requirements and protocol error handling. Be part of industry standards bodies and work groups to keep Eliyan's product implementations up to date with the latest versions of the standards.
Leadership:
Mentor engineers on protocol implementation, timing constraints, and hierarchical design. Effectively collaborate with industry technologists, business leaders and ability to network seamlessly with industry peers to influence stakeholders.
Minimum Qualifications
Expertise in multiple areas of architecture definition, chip micro‑architecture, protocol definition and implementation
Strong knowledge of two or more of the following connectivity protocols - PCIe, UCIe, UALink, Ethernet, DDR, AMBA
Strong scripting and automation skills
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
8+ years’ of experience
Ideal Qualifications
15+ years of experience in ASIC architecture with strong bias for practical logic design and influence of physical implementation, with a proven track record of leading teams through successful tapeouts
Performance modeling of hardware implementations with high level languages like C, C++ or SystemC
Adept at clocking and floorplan guidelines for PHY implementation
Extremely knowledgeable on RTL-to-GDSII flows, limitations, and flexibilities to improve productivity and power aware designs
Exceptional problem‑solving skills.
#J-18808-Ljbffr