Senior Silicon PD Engineer, TPU – ML Accelerator

A global technology company in Mountain View is seeking a Senior Silicon Physical Design Engineer to lead physical design methodologies. This role requires 5+ years of advanced design experience, particularly in SoC cycles and low power designs. The ideal candidate holds a Bachelor’s or Master’s in Electrical Engineering and is skilled in System Verilog and TCL scripting. You'll drive innovations that power the next generation of hardware across Google's data centers. #J-18808-Ljbffr