NVIDIA
Overview
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Join us today. The clocks group is looking for a top‑notch ASIC engineer to join the team. The team is responsible for crafting all aspects of GPU and CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the chip. The clocks team interacts with the floor‑planning and back end team to help craft the physical floorplan of the chip. The team explains the programming model to the SW team to come up with an efficient clock programming sequence. The team works with the silicon solution team to triage silicon or programming bugs in the lab. Responsibilities
Architect the clock domain to satisfy functional, physical and testing design requirements. Engage with multiple teams and design the GPU or CPU clocks to satisfy all the architectural/design/physical constraints. Improve Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade‑offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL. Collaborate with Physical Design and timing team to evaluate Clocking concerns and develop solutions for supporting high speed Clocking. Deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams. Get involved in end‑to‑end cycle of ASIC execution starting from micro‑arch, design implementation, design fixes, sign‑off checks and all the way to Silicon bring‑up. Qualifications
BS in Electrical Engineering or equivalent experience (MS preferred). 3+ years of relevant work experience. Deep understanding of logic optimization techniques and PPA trade‑offs. Excellent interpersonal skills and ability to collaborate with multiple teams. Experience in RTL design (Verilog), verification and logic synthesis. Strong coding skills in python or other industry‑standard scripting languages. Understanding of sub‑micron silicon issues like noise, cross‑talk, and OCV effects is a plus. Implementing on‑chip clocking networks is a bonus. Ways to Stand Out
Experience with clocks controller, clocks logic design. Understanding of system level artifacts like power, noise, etc. Experience with scalable designs and architecture. Hands‑on silicon debug is a plus. Benefits & Compensation
We offer competitive salaries and a generous benefits package. Base salary ranges are $136,000 – $212,750 for Level 3 and $168,000 – $264,500 for Level 4, adjusted for location and experience. You will also be eligible for equity and benefits. Applications for this job will be accepted until December 16, 2025. Equal Opportunity
NVIDIA is committed to fostering a diverse work environment and is an equal‑opportunity employer. NVIDIA does not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Join us today. The clocks group is looking for a top‑notch ASIC engineer to join the team. The team is responsible for crafting all aspects of GPU and CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the chip. The clocks team interacts with the floor‑planning and back end team to help craft the physical floorplan of the chip. The team explains the programming model to the SW team to come up with an efficient clock programming sequence. The team works with the silicon solution team to triage silicon or programming bugs in the lab. Responsibilities
Architect the clock domain to satisfy functional, physical and testing design requirements. Engage with multiple teams and design the GPU or CPU clocks to satisfy all the architectural/design/physical constraints. Improve Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade‑offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL. Collaborate with Physical Design and timing team to evaluate Clocking concerns and develop solutions for supporting high speed Clocking. Deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams. Get involved in end‑to‑end cycle of ASIC execution starting from micro‑arch, design implementation, design fixes, sign‑off checks and all the way to Silicon bring‑up. Qualifications
BS in Electrical Engineering or equivalent experience (MS preferred). 3+ years of relevant work experience. Deep understanding of logic optimization techniques and PPA trade‑offs. Excellent interpersonal skills and ability to collaborate with multiple teams. Experience in RTL design (Verilog), verification and logic synthesis. Strong coding skills in python or other industry‑standard scripting languages. Understanding of sub‑micron silicon issues like noise, cross‑talk, and OCV effects is a plus. Implementing on‑chip clocking networks is a bonus. Ways to Stand Out
Experience with clocks controller, clocks logic design. Understanding of system level artifacts like power, noise, etc. Experience with scalable designs and architecture. Hands‑on silicon debug is a plus. Benefits & Compensation
We offer competitive salaries and a generous benefits package. Base salary ranges are $136,000 – $212,750 for Level 3 and $168,000 – $264,500 for Level 4, adjusted for location and experience. You will also be eligible for equity and benefits. Applications for this job will be accepted until December 16, 2025. Equal Opportunity
NVIDIA is committed to fostering a diverse work environment and is an equal‑opportunity employer. NVIDIA does not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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