Google
About The Job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google’s direct‑to‑consumer products. You’ll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Chip Package Designer on the Silicon Integration team, your role is to develop package substrate designs of advanced (2.5D/3.5D) packaging technologies for ML chips. This involves collaborating with SI/PI (Signal Integrity/Power Integrity), thermal/mechanical, assembly, and PCB engineers to create complex, high‑performance substrate designs. The goal is to optimize package substrate design for electrical performance, reliability, and assembly. In this role, you will manage all phases of the design process, including routing feasibility, test vehicle creation, product designs, conducting design reviews, artwork export, DFM process and generating final documentation. Additionally, you will be instrumental in identifying and incorporating advanced chip packaging technologies into the Google chip product design pipeline, contributing to successful chip deployment in data centers and enhancing system performance relative to TCO and power. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services and Google Cloud. We prioritize security, efficiency, and reliability across everything we do. US base salary range for this full‑time position is $156,000–$229,000 + bonus + equity + benefits. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Responsibilities
Manage physical package substrate design of large form‑factor package for ML High‑Performance Computers (HPCs). Develop and implement the methodology and CAD flow for efficient substrate design and enhanced productivity. Manage and drive co‑design initiatives across chip, package, and system levels, including securing production sign‑off for package designs. Collaborate closely with SI/PI, Thermal, and Mechanical Engineering teams to refine and optimize product package designs, test vehicles, and mock‑up designs for product feasibility. Define and document the requirements for the package substrate design and Bill of Materials (BOM). Minimum Qualifications
Bachelor’s degree in Mechanical, Material, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience. 4 years of experience in chip package substrate design using Cadence APD (Allegro Package Designer) or Mentor Expedition. Experience in chip package substrate layout, design verification, DFM, and taping‑out for production. Experience in design automation and scripting. Preferred Qualifications
Experience in large‑scale 2.5D/3.5D advanced package design. Experience in working with cross‑functional teams including chip design, SI/PI, and PCB design teams. Experience in physical verification flow (e.g., LVS, DRC, connectivity). Experience with CAD for creating simple mechanical drawings, such as Package Outline Drawings (POD). Ability to write scripts to customize elements of the Cadence or Mentor workflow. Google is proud to be an equal‑opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
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Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google’s direct‑to‑consumer products. You’ll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Chip Package Designer on the Silicon Integration team, your role is to develop package substrate designs of advanced (2.5D/3.5D) packaging technologies for ML chips. This involves collaborating with SI/PI (Signal Integrity/Power Integrity), thermal/mechanical, assembly, and PCB engineers to create complex, high‑performance substrate designs. The goal is to optimize package substrate design for electrical performance, reliability, and assembly. In this role, you will manage all phases of the design process, including routing feasibility, test vehicle creation, product designs, conducting design reviews, artwork export, DFM process and generating final documentation. Additionally, you will be instrumental in identifying and incorporating advanced chip packaging technologies into the Google chip product design pipeline, contributing to successful chip deployment in data centers and enhancing system performance relative to TCO and power. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services and Google Cloud. We prioritize security, efficiency, and reliability across everything we do. US base salary range for this full‑time position is $156,000–$229,000 + bonus + equity + benefits. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Responsibilities
Manage physical package substrate design of large form‑factor package for ML High‑Performance Computers (HPCs). Develop and implement the methodology and CAD flow for efficient substrate design and enhanced productivity. Manage and drive co‑design initiatives across chip, package, and system levels, including securing production sign‑off for package designs. Collaborate closely with SI/PI, Thermal, and Mechanical Engineering teams to refine and optimize product package designs, test vehicles, and mock‑up designs for product feasibility. Define and document the requirements for the package substrate design and Bill of Materials (BOM). Minimum Qualifications
Bachelor’s degree in Mechanical, Material, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience. 4 years of experience in chip package substrate design using Cadence APD (Allegro Package Designer) or Mentor Expedition. Experience in chip package substrate layout, design verification, DFM, and taping‑out for production. Experience in design automation and scripting. Preferred Qualifications
Experience in large‑scale 2.5D/3.5D advanced package design. Experience in working with cross‑functional teams including chip design, SI/PI, and PCB design teams. Experience in physical verification flow (e.g., LVS, DRC, connectivity). Experience with CAD for creating simple mechanical drawings, such as Package Outline Drawings (POD). Ability to write scripts to customize elements of the Cadence or Mentor workflow. Google is proud to be an equal‑opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
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