Meta
Design Verification Engineer – Meta
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Design Verification Engineer
role at
Meta .
Reality Labs focuses on delivering Meta's vision through AI-first devices that leverage our wearable technologies. The compute performance and power efficiency requirements require custom silicon. We are driving the state-of-the-art forward with highly integrated SoCs that leverage breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable Meta’s Wearable devices that blend our real and virtual worlds throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms.
Responsibilities
Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification.
Develop functional tests based on verification test plan.
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
Debug, root‑cause and resolve functional failures in the design, partnering with the Design team.
Collaborate with cross‑functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.
Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.
Minimum Qualifications
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
6+ years of hands‑on experience in SystemVerilog/UVM methodology and/or C/C++ based verification.
6+ years of experience in IP/sub‑system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.
Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.
Preferred Qualifications
Experience with revision control systems like Mercurial(Hg), Git or SVN.
Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle.
Experience in development of Universal Verification Methodology (UVM) based verification environments from scratch.
Experience in one or more of the following areas: SystemVerilog Assertions (SVA), Formal, and Emulation.
Prior working knowledge of Audio/image/Video processing compute intensive cores.
Compensation and Benefits Base pay range: $142,000.00/yr - $203,000.00/yr. Additional bonus, equity and benefits applicable.
About Meta Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.
Equal Employment Opportunity Meta is a proud Equal Employment Opportunity and affirmative action employer. We do not discriminate based on race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E‑Verify program where required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Accommodations Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.
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Design Verification Engineer
role at
Meta .
Reality Labs focuses on delivering Meta's vision through AI-first devices that leverage our wearable technologies. The compute performance and power efficiency requirements require custom silicon. We are driving the state-of-the-art forward with highly integrated SoCs that leverage breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable Meta’s Wearable devices that blend our real and virtual worlds throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms.
Responsibilities
Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification.
Develop functional tests based on verification test plan.
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
Debug, root‑cause and resolve functional failures in the design, partnering with the Design team.
Collaborate with cross‑functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.
Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.
Minimum Qualifications
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
6+ years of hands‑on experience in SystemVerilog/UVM methodology and/or C/C++ based verification.
6+ years of experience in IP/sub‑system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.
Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.
Preferred Qualifications
Experience with revision control systems like Mercurial(Hg), Git or SVN.
Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle.
Experience in development of Universal Verification Methodology (UVM) based verification environments from scratch.
Experience in one or more of the following areas: SystemVerilog Assertions (SVA), Formal, and Emulation.
Prior working knowledge of Audio/image/Video processing compute intensive cores.
Compensation and Benefits Base pay range: $142,000.00/yr - $203,000.00/yr. Additional bonus, equity and benefits applicable.
About Meta Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.
Equal Employment Opportunity Meta is a proud Equal Employment Opportunity and affirmative action employer. We do not discriminate based on race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E‑Verify program where required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Accommodations Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.
#J-18808-Ljbffr