Astera Labs
Principal Analog Mixed-Signal CAD Engineer
Astera Labs, San Jose, California, United States, 95199
Principal Analog Mixed-Signal CAD Engineer
San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . About the Role
We are seeking a Principal CAD Engineer to architect, build, and maintain an integrated CAD infrastructure that enables seamless collaboration across analog/mixed-signal (AMS), digital RTL, physical design, and verification/validation teams. You will be the technical owner for cross-domain design environments ensuring reliability, scalability, and reproducibility across IP and SoC programs. This role combines EDA flow knowledge, and methodology knowledge. You will partner with design and verification leaders to define best practices, establish flows, and deliver a first-class designer experience from concept to tape-out. Key Responsibilities
CAD tools Ownership Flow Development and Methodology Compute infrastructure and Automation Cross-Functional Enablement and Support Tape-out Readiness and Sign-off Required Qualifications & Experience
10+ years in CAD/EDA methodology development for IP/SoC programs across AMS and digital domains (advanced nodes preferred: 7 nm → 3 nm or equivalent). Deep hands-on expertise with major EDA ecosystems (Cadence, Synopsys, Siemens). Strong scripting/automation: Python, Perl, shell scripting, Cadence Skill, Tcl Version control and data management: Git/Perforce Understanding of timing verification, SI, EM/IR, physical verification, library/PDK fundamentals, and foundry deliverables. Core Competencies & Skills
End-to-end flow integration across AMS, digital, PD, and verification disciplines. Performance tuning: distributed resource management, memory/CPU/GPU utilization, and license efficiency. Ability to abstract complex flows into modular components and standard interfaces. Influence across organizations; mentor junior CAD engineers and power users. Clear documentation, and effective training for current and new team members. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. Apply for this job
Please apply via our careers page.
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San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . About the Role
We are seeking a Principal CAD Engineer to architect, build, and maintain an integrated CAD infrastructure that enables seamless collaboration across analog/mixed-signal (AMS), digital RTL, physical design, and verification/validation teams. You will be the technical owner for cross-domain design environments ensuring reliability, scalability, and reproducibility across IP and SoC programs. This role combines EDA flow knowledge, and methodology knowledge. You will partner with design and verification leaders to define best practices, establish flows, and deliver a first-class designer experience from concept to tape-out. Key Responsibilities
CAD tools Ownership Flow Development and Methodology Compute infrastructure and Automation Cross-Functional Enablement and Support Tape-out Readiness and Sign-off Required Qualifications & Experience
10+ years in CAD/EDA methodology development for IP/SoC programs across AMS and digital domains (advanced nodes preferred: 7 nm → 3 nm or equivalent). Deep hands-on expertise with major EDA ecosystems (Cadence, Synopsys, Siemens). Strong scripting/automation: Python, Perl, shell scripting, Cadence Skill, Tcl Version control and data management: Git/Perforce Understanding of timing verification, SI, EM/IR, physical verification, library/PDK fundamentals, and foundry deliverables. Core Competencies & Skills
End-to-end flow integration across AMS, digital, PD, and verification disciplines. Performance tuning: distributed resource management, memory/CPU/GPU utilization, and license efficiency. Ability to abstract complex flows into modular components and standard interfaces. Influence across organizations; mentor junior CAD engineers and power users. Clear documentation, and effective training for current and new team members. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. Apply for this job
Please apply via our careers page.
#J-18808-Ljbffr