SpaceX
Sr. ASIC Design Engineer (Silicon Engineering)
SpaceX, Sunnyvale, California, United States, 94087
Senior ASIC Design Engineer (Silicon Engineering)
SpaceX is developing the technologies to enable human life on Mars. Starlink, the world’s largest satellite constellation, provides fast, reliable internet to millions of users worldwide.
Overview We are seeking a motivated, proactive, and intellectually curious engineer to work alongside world‑class cross‑disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role you will develop next‑generation FPGAs and ASICs for deployment in space and ground infrastructures.
Responsibilities
Evaluate architectural trade‑offs based on features, performance requirements, and system limitations.
Define micro‑architecture, implement RTL in Verilog/System‑Verilog, and deliver fully verified, synthesis/timing‑clean design.
Work closely with verification team to ensure all aspects of the design are covered and verified.
Provide timing constraints for IPs and support physical implementation team (synthesis, timing closure, formality check).
Participate in silicon bring‑up and validation.
Basic Qualifications
Bachelor’s degree in electrical engineering, computer engineering, or computer science.
5+ years of experience in RTL implementation.
Preferred Skills and Experience
Ability to solve complex problems including clock domain crossings and power optimization.
ASIC/SoC system integration experience.
Experience with multicore CPU subsystem design.
Experience with standard bus protocols (e.g., AXI, AHB, etc.).
Experience with embedded processors.
Experience with high speed and low power design techniques.
Scripting skills (Python, TCL, etc.).
Experience with EDA tools such as HDL simulators (VCS, Questa, IES), HDL lint tools (Spyglass), and FPGA tools (Vivado, Quartus II).
Ability to work in a dynamic environment with changing needs and requirements.
Team‑player, can‑do attitude, and ability to work well in a group while contributing individually.
Enjoys being challenged and learning new skills.
Additional Requirements
Must be willing to work extended hours and weekends as needed.
Compensation & Benefits Pay Range:
$170,000.00 – $230,000.00 per year.
Base salary is one part of your total rewards package. Eligible for stock, long‑term incentives, discretionary bonuses, stock purchase plan, medical/vision/dental coverage, 401(k), disability, life insurance, paid parental leave, discounts, 3 weeks paid vacation, 10+ paid holidays, sick leave.
Export Regulations (ITAR)
Applicant must be a U.S. citizen or national, lawful permanent resident (green card holder), refugee, or asylee, or eligible to obtain required authorizations from the U.S. Department of State.
Equal Opportunity Employer SpaceX is an Equal Opportunity Employer. Employment is governed by merit, competence, and qualifications and is not influenced by protected status. For reasonable accommodations, contact EEOCompliance@spacex.com.
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Overview We are seeking a motivated, proactive, and intellectually curious engineer to work alongside world‑class cross‑disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role you will develop next‑generation FPGAs and ASICs for deployment in space and ground infrastructures.
Responsibilities
Evaluate architectural trade‑offs based on features, performance requirements, and system limitations.
Define micro‑architecture, implement RTL in Verilog/System‑Verilog, and deliver fully verified, synthesis/timing‑clean design.
Work closely with verification team to ensure all aspects of the design are covered and verified.
Provide timing constraints for IPs and support physical implementation team (synthesis, timing closure, formality check).
Participate in silicon bring‑up and validation.
Basic Qualifications
Bachelor’s degree in electrical engineering, computer engineering, or computer science.
5+ years of experience in RTL implementation.
Preferred Skills and Experience
Ability to solve complex problems including clock domain crossings and power optimization.
ASIC/SoC system integration experience.
Experience with multicore CPU subsystem design.
Experience with standard bus protocols (e.g., AXI, AHB, etc.).
Experience with embedded processors.
Experience with high speed and low power design techniques.
Scripting skills (Python, TCL, etc.).
Experience with EDA tools such as HDL simulators (VCS, Questa, IES), HDL lint tools (Spyglass), and FPGA tools (Vivado, Quartus II).
Ability to work in a dynamic environment with changing needs and requirements.
Team‑player, can‑do attitude, and ability to work well in a group while contributing individually.
Enjoys being challenged and learning new skills.
Additional Requirements
Must be willing to work extended hours and weekends as needed.
Compensation & Benefits Pay Range:
$170,000.00 – $230,000.00 per year.
Base salary is one part of your total rewards package. Eligible for stock, long‑term incentives, discretionary bonuses, stock purchase plan, medical/vision/dental coverage, 401(k), disability, life insurance, paid parental leave, discounts, 3 weeks paid vacation, 10+ paid holidays, sick leave.
Export Regulations (ITAR)
Applicant must be a U.S. citizen or national, lawful permanent resident (green card holder), refugee, or asylee, or eligible to obtain required authorizations from the U.S. Department of State.
Equal Opportunity Employer SpaceX is an Equal Opportunity Employer. Employment is governed by merit, competence, and qualifications and is not influenced by protected status. For reasonable accommodations, contact EEOCompliance@spacex.com.
#J-18808-Ljbffr