ACL Digital
Physical Design Engineer
We are seeking a skilled Physical Design Engineer to implement high-performance RISC‑V based processor designs from RTL to GDSII. The role involves full‑chip and block‑level physical implementation, timing closure, power optimization, PPA and sign‑off.
Qualification and Required skills:
At least 8 Years of Experience in Block-level physical implementation from RTL to GDSII
Own advanced physical design tasks including: EM/IR and power grid optimization for high-current blocks, congestion mitigation and routing-aware floorplanning and clock tree synthesis and skew management across domains.
Drive signoff closure: DRC, LVS, antenna, ERC, and tapeout readiness using industry-standard tools (e.g., Innovus, ICC2, Calibre, Voltus, RedHawk).
Contribute to and improve physical design automation infrastructure using Tcl, Python, Perl, and other scripting tools.
Referrals increase your chances of interviewing at ACL Digital by 2x.
#J-18808-Ljbffr
Qualification and Required skills:
At least 8 Years of Experience in Block-level physical implementation from RTL to GDSII
Own advanced physical design tasks including: EM/IR and power grid optimization for high-current blocks, congestion mitigation and routing-aware floorplanning and clock tree synthesis and skew management across domains.
Drive signoff closure: DRC, LVS, antenna, ERC, and tapeout readiness using industry-standard tools (e.g., Innovus, ICC2, Calibre, Voltus, RedHawk).
Contribute to and improve physical design automation infrastructure using Tcl, Python, Perl, and other scripting tools.
Referrals increase your chances of interviewing at ACL Digital by 2x.
#J-18808-Ljbffr