Intel Corporation
Overview
DFT Design Engineer role at Intel Corporation. This posting outlines responsibilities and qualifications for the DFT design engineer position. Responsibilities
Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN). Collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST). Develops high-volume manufacturing (HVM) content for rapid bring-up and ramp to production on automated test equipment (ATE). Writes and generates RTL and structural code to integrate DFT using various strategies, tools, and methods. Optimizes logic to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals while preserving design integrity for physical implementation. Reviews the verification plan and drives verification of the DFT design to meet architecture and microarchitecture specifications. Ensures design features are verified correctly and implements corrective measures for failing RTL tests to ensure feature correctness. Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high-quality IP integration. Collaborates with post-silicon and manufacturing teams to verify features on silicon, support debug requirements, and document learnings and improvements in design and validation. Drives high test coverage through structural and targeted IP tests to achieve quality and DPM objectives, and develops HVM content for rapid bring-up and production on the ATE. Qualifications
Minimum Qualifications Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 4+ years of relevant experience Or Master’s degree in the same fields with 3+ years of relevant experience Or PhD in the same fields with 6+ months of relevant experience Relevant Work Experience Should Be Of The Following Experience with DFT Array Test including MBIST or SCAN/ATPG or DFT Verification Preferred Qualifications Expertise in Tessent DFT tool Expertise in Primetime, especially in DFT constraints Expertise in Quality checks such as Lint, VCLP, CDC/RDC, LEC, Spyglass DFT Job Details
Job Type:
Experienced Hire Shift:
Shift 1 (United States of America) Primary Location:
US, California, Santa Clara Additional Locations:
US, Oregon, Hillsboro; US, Texas, Austin Business Group
At the Data Center Group (DCG), we’re committed to delivering exceptional products and delighting our customers. We offer broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload-driven leadership products and collaboration with our partners. Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, ancestry, age, disability, genetic information, military status, marital status, pregnancy, gender identity or expression, sexual orientation, or any other characteristic protected by law. Work Model for this Role
This role will require on-site presence. Job posting details (such as work model, location or time type) are subject to change.
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DFT Design Engineer role at Intel Corporation. This posting outlines responsibilities and qualifications for the DFT design engineer position. Responsibilities
Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN). Collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST). Develops high-volume manufacturing (HVM) content for rapid bring-up and ramp to production on automated test equipment (ATE). Writes and generates RTL and structural code to integrate DFT using various strategies, tools, and methods. Optimizes logic to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals while preserving design integrity for physical implementation. Reviews the verification plan and drives verification of the DFT design to meet architecture and microarchitecture specifications. Ensures design features are verified correctly and implements corrective measures for failing RTL tests to ensure feature correctness. Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high-quality IP integration. Collaborates with post-silicon and manufacturing teams to verify features on silicon, support debug requirements, and document learnings and improvements in design and validation. Drives high test coverage through structural and targeted IP tests to achieve quality and DPM objectives, and develops HVM content for rapid bring-up and production on the ATE. Qualifications
Minimum Qualifications Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 4+ years of relevant experience Or Master’s degree in the same fields with 3+ years of relevant experience Or PhD in the same fields with 6+ months of relevant experience Relevant Work Experience Should Be Of The Following Experience with DFT Array Test including MBIST or SCAN/ATPG or DFT Verification Preferred Qualifications Expertise in Tessent DFT tool Expertise in Primetime, especially in DFT constraints Expertise in Quality checks such as Lint, VCLP, CDC/RDC, LEC, Spyglass DFT Job Details
Job Type:
Experienced Hire Shift:
Shift 1 (United States of America) Primary Location:
US, California, Santa Clara Additional Locations:
US, Oregon, Hillsboro; US, Texas, Austin Business Group
At the Data Center Group (DCG), we’re committed to delivering exceptional products and delighting our customers. We offer broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload-driven leadership products and collaboration with our partners. Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, ancestry, age, disability, genetic information, military status, marital status, pregnancy, gender identity or expression, sexual orientation, or any other characteristic protected by law. Work Model for this Role
This role will require on-site presence. Job posting details (such as work model, location or time type) are subject to change.
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