General Dynamics Corporation
FPGA Design Engineer
General Dynamics Corporation, Sterling Heights, Michigan, United States, 48310
Job Details
Position Title:
FPGA Design Engineer
Location:
Sterling Heights, MI, United States
Category:
Engineering
Job Type:
Contract
Country:
United States
State:
MI
City:
Sterling Heights
Remote Work Options:
On-Site
Security Clearance Required:
Ability to obtain security clearance
Career Level:
Senior
Requisition ID:
17123257
About the Role The Field Programmable Gate Array (FPGA) Design Engineer position is responsible for electronics and FPGA design, implementation in support of video and image processing.
Responsibilities
Collaborating with systems, software, and hardware engineers to develop FPGA designs for video processing, control systems, and system interfaces
Support existing and/or legacy FPGA designs
Develop and review requirements and digest into work packages
Collaborate with teams through issue tracking and use of revision control systems
Implement designs using existing IP blocks from Xilinx and other third-party vendors
Create new IP in VHDL, Verilog
Develop system constraints and perform timing closure
Perform debug through simulation and physical lab testing
Position Requirements
Bachelor's degree (B.A. or B.S.) in Electrical or Computer Engineering or Computer Science
10+ years of experience
Experience with Git or similar revision control systems
Experience with Jira or similar issue tracking systems
Experience with designing ARM processors and AXI bus with Zynq Ultrascale+ MPSoC or understanding similar SoC FPGA architectures, including the PS-PL interfacing, either on bare‑C or OS based designs
Experience with industry‑standard protocols, such as PCIe, USB, Ethernet, DDR, I2C, SPI, CAN, etc.
Experience with generic video and camera interfaces such as LVDS, HDMI, Display Port, Camera Link, SDI, GigEVision, etc.
Experience with Xilinx tool chain; Vivado, SDK, Vitis
Equal Opportunity Employer As an Equal Opportunity Employer, General Dynamics Land Systems ("GDLS") provides all persons with equal opportunity and access to all aspects of employment process, without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, marital status, age, disability, status as a protected veteran, or membership in any group protected by federal, state, or local anti‑discrimination laws. GDLS also is committed to providing reasonable accommodations to individuals with disabilities and disabled veterans. If, due to a disability, you need an accommodation to search or apply for an opportunity with GDLS, please call 586-825-4000 or send an e‑mail for assistance and let us know the nature of your request and your contact information.
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FPGA Design Engineer
Location:
Sterling Heights, MI, United States
Category:
Engineering
Job Type:
Contract
Country:
United States
State:
MI
City:
Sterling Heights
Remote Work Options:
On-Site
Security Clearance Required:
Ability to obtain security clearance
Career Level:
Senior
Requisition ID:
17123257
About the Role The Field Programmable Gate Array (FPGA) Design Engineer position is responsible for electronics and FPGA design, implementation in support of video and image processing.
Responsibilities
Collaborating with systems, software, and hardware engineers to develop FPGA designs for video processing, control systems, and system interfaces
Support existing and/or legacy FPGA designs
Develop and review requirements and digest into work packages
Collaborate with teams through issue tracking and use of revision control systems
Implement designs using existing IP blocks from Xilinx and other third-party vendors
Create new IP in VHDL, Verilog
Develop system constraints and perform timing closure
Perform debug through simulation and physical lab testing
Position Requirements
Bachelor's degree (B.A. or B.S.) in Electrical or Computer Engineering or Computer Science
10+ years of experience
Experience with Git or similar revision control systems
Experience with Jira or similar issue tracking systems
Experience with designing ARM processors and AXI bus with Zynq Ultrascale+ MPSoC or understanding similar SoC FPGA architectures, including the PS-PL interfacing, either on bare‑C or OS based designs
Experience with industry‑standard protocols, such as PCIe, USB, Ethernet, DDR, I2C, SPI, CAN, etc.
Experience with generic video and camera interfaces such as LVDS, HDMI, Display Port, Camera Link, SDI, GigEVision, etc.
Experience with Xilinx tool chain; Vivado, SDK, Vitis
Equal Opportunity Employer As an Equal Opportunity Employer, General Dynamics Land Systems ("GDLS") provides all persons with equal opportunity and access to all aspects of employment process, without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, marital status, age, disability, status as a protected veteran, or membership in any group protected by federal, state, or local anti‑discrimination laws. GDLS also is committed to providing reasonable accommodations to individuals with disabilities and disabled veterans. If, due to a disability, you need an accommodation to search or apply for an opportunity with GDLS, please call 586-825-4000 or send an e‑mail for assistance and let us know the nature of your request and your contact information.
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