Lockheed Martin Corporation
ASIC/FPGA Design Engineer III
Lockheed Martin Corporation, Highlands Ranch, Colorado, United States
ASIC/FPGA Design Engineer
Join Our Team as a
ASIC/FPGA Design Engineer
where you will work on the development of a sophisticated state‑of‑the‑art avionics product in a world class Integrated Product Development environment.
Location This position does not support teleworking; the selected candidate will be located near our Lockheed Martin Space facility in Denver CO or Highlands Ranch CO, Sunnyvale CA.
About Lockheed Martin Space Space is a critical domain, connecting our technologies, our security, and our humanity. While others view space as a destination, we see it as a realm of possibilities, where we can do more – we can innovate, invest, inspire, and integrate our capabilities to transform the future.
What does this role look like? The Silicon Solutions team of Lockheed Martin Space is building the best ASIC/FPGA team in the world, and are seeking a highly talented and motivated ASIC & FPGA Design Engineer who has a passion for microchip design and space. You will be working at the Supplier site in Cambridge MA.
Key activities you will accomplish in this role:
Work with low SWaP, radiation hardened, space‑rated devices.
Perform all aspects of ASIC and FPGA development through the lifecycle from initial requirements capture through architecture, design, analysis, simulations and test in a Linux‑based high‑performance computing environment.
Support technical reviews and present to internal and external stakeholders.
Interface with an independent verification team who will be working in parallel, verifying the design.
To be effective in this role, you will need:
Independently minded and well organized engineer, comfortable in laboratory digital environments, able to respond and interact with a dynamic fast‑moving team.
3 years professional experience.
Obtain and maintain a DoD Secret clearance (ship required).
Basic Qualifications
Bachelor of Science or higher from an accredited college in Electrical Engineering or related discipline, or equivalent experience/combined education.
Experience in the design of FPGAs, Digital ASICs, Mixed‑signal ASICs.
HDL programming experience with VHDL, Verilog, and/or SystemVerilog.
Linux development environment.
Willing and able to obtain and maintain a DoD Secret clearance (ship required).
Desired skills
Experience in ASIC / FPGA life cycle (architecture, design, simulation, verification, validation, integration & test).
FPGA/ASIC verification experience is a plus.
Experience with electronics design.
Experience in lab integration and troubleshooting activities.
Knowledge of space‑grade/qualified FPGAs and ASICs and toolsets including AMD/Xilinx Vivado or Microchip Libero.
Experience with MS Project, JIRA.
Experience with Earned Value Management System (EVMS).
EEO Lockheed Martin is an equal opportunity employer. Qualified candidates will be considered without regard to legally protected characteristics.
Application Window The application window will close in 90 days; applicants are encouraged to apply within 5–30 days of the requisition posting date to receive optimal consideration.
#J-18808-Ljbffr
ASIC/FPGA Design Engineer
where you will work on the development of a sophisticated state‑of‑the‑art avionics product in a world class Integrated Product Development environment.
Location This position does not support teleworking; the selected candidate will be located near our Lockheed Martin Space facility in Denver CO or Highlands Ranch CO, Sunnyvale CA.
About Lockheed Martin Space Space is a critical domain, connecting our technologies, our security, and our humanity. While others view space as a destination, we see it as a realm of possibilities, where we can do more – we can innovate, invest, inspire, and integrate our capabilities to transform the future.
What does this role look like? The Silicon Solutions team of Lockheed Martin Space is building the best ASIC/FPGA team in the world, and are seeking a highly talented and motivated ASIC & FPGA Design Engineer who has a passion for microchip design and space. You will be working at the Supplier site in Cambridge MA.
Key activities you will accomplish in this role:
Work with low SWaP, radiation hardened, space‑rated devices.
Perform all aspects of ASIC and FPGA development through the lifecycle from initial requirements capture through architecture, design, analysis, simulations and test in a Linux‑based high‑performance computing environment.
Support technical reviews and present to internal and external stakeholders.
Interface with an independent verification team who will be working in parallel, verifying the design.
To be effective in this role, you will need:
Independently minded and well organized engineer, comfortable in laboratory digital environments, able to respond and interact with a dynamic fast‑moving team.
3 years professional experience.
Obtain and maintain a DoD Secret clearance (ship required).
Basic Qualifications
Bachelor of Science or higher from an accredited college in Electrical Engineering or related discipline, or equivalent experience/combined education.
Experience in the design of FPGAs, Digital ASICs, Mixed‑signal ASICs.
HDL programming experience with VHDL, Verilog, and/or SystemVerilog.
Linux development environment.
Willing and able to obtain and maintain a DoD Secret clearance (ship required).
Desired skills
Experience in ASIC / FPGA life cycle (architecture, design, simulation, verification, validation, integration & test).
FPGA/ASIC verification experience is a plus.
Experience with electronics design.
Experience in lab integration and troubleshooting activities.
Knowledge of space‑grade/qualified FPGAs and ASICs and toolsets including AMD/Xilinx Vivado or Microchip Libero.
Experience with MS Project, JIRA.
Experience with Earned Value Management System (EVMS).
EEO Lockheed Martin is an equal opportunity employer. Qualified candidates will be considered without regard to legally protected characteristics.
Application Window The application window will close in 90 days; applicants are encouraged to apply within 5–30 days of the requisition posting date to receive optimal consideration.
#J-18808-Ljbffr