Remote Senior RTL Design Engineer — Floating Point

A technology firm is seeking a Senior RTL Design Engineer to handle floating-point architecture. This role encompasses designing high-performance RTL modules using Verilog, collaborating with microarchitecture teams, and ensuring functional correctness of datapaths. Ideal candidates will have over 8 years of experience in ASIC or FPGA design, strong knowledge of IEEE 754 standards, and proficiency in simulation tools. This position offers a competitive salary of $140k-$160k annually, alongside full-time employee benefits including comprehensive medical coverage, PTO, and retirement plans. #J-18808-Ljbffr