Vivid Technology
Senior Digital IC Design Engineer
Vivid Technology, San Jose, California, United States, 95199
1 day ago Be among the first 25 applicants
Get AI-powered advice on this job and more exclusive features.
Direct message the job poster from Vivid Technology
This high-growth start-up is revolutionizing automotive perception technology. With next-generation sensors, they are redefining the capabilities of imaging radar, delivering unprecedented resolution and performance. Their team is passionate about pushing the boundaries of sensor technology.
Key Qualifications
10+ years hands‑on experience in digital design with the understanding of analog and mixed‑signal IC design, ideally in CMOS technologies at 28nm TSMC Expertise in the following: SPI/I2C or other high speed digital interfaces, bandgap design, temperature sensors, biasing circuits, IFM, PGA, power detection, or diagnostic ADCs Strong experience with RTL design in Verilog/SystemVerilog Proficiency with digital simulation and debug tools (Questa, VCS, Xcelium, etc.) Familiarity with synthesis, STA, and power‑aware design flows Solid background in low‑power design methodologies and tradeoffs Proficiency with Cadence Virtuoso, Spectre, and AMS simulation tools Experience with lab validation, silicon debug, and characterization MS or Ph.D. in Electrical Engineering or equivalent Responsibilities
Define and architect digital subsystems within RFICs Partition functionality between analog, mixed‑signal, and digital domains to optimize performance, area, and power Develop subsystem‑level digital specifications in collaboration with RF, analog, and systems teams Own register/memory maps, digital interfaces, and configuration settings, diagnostic / test profiles Own the digital design and ensure design meets PVT, reliability, and automotive quality standards (FuSa, AEC‑Q100, ISO 26262) Support synthesis, STA, clock‑domain crossing, low‑power design, and DFT with physical design teams Ensure robustness across PVT, ESD, reliability, and automotive qualification corners (if applicable) Review ECOs, timing fixes, and power optimization strategies Lead activities for the design and implement high‑performance, low‑power analog and mixed‑signal blocks e.g. bandgap references, temperature sensors, diagnostic ADCs, programmable gain amplifiers, power detectors, bias circuits Derive block‑level specifications from system requirements and contribute to architecture discussions Own schematic design, pre‑/post‑layout simulation, and verification using industry‑standard EDA tools Collaborate with layout engineers to ensure robust and efficient physical design Support silicon bring‑up, validation, and debug in the lab Partner with RF, digital, and systems engineers to enable seamless integration of mixed‑signal IP into the overall sensor SoC Bonus: prior exposure to sensor products, or radar‑based systems Benefits
Medical insurance Vision insurance 401(k) Pension plan Paid paternity leave Paid maternity leave Tuition assistance San Jose, CA $80,000.00-$110,000.00 5 days ago Sunnyvale, CA $118,000.00-$170,000.00 2 weeks ago
#J-18808-Ljbffr
10+ years hands‑on experience in digital design with the understanding of analog and mixed‑signal IC design, ideally in CMOS technologies at 28nm TSMC Expertise in the following: SPI/I2C or other high speed digital interfaces, bandgap design, temperature sensors, biasing circuits, IFM, PGA, power detection, or diagnostic ADCs Strong experience with RTL design in Verilog/SystemVerilog Proficiency with digital simulation and debug tools (Questa, VCS, Xcelium, etc.) Familiarity with synthesis, STA, and power‑aware design flows Solid background in low‑power design methodologies and tradeoffs Proficiency with Cadence Virtuoso, Spectre, and AMS simulation tools Experience with lab validation, silicon debug, and characterization MS or Ph.D. in Electrical Engineering or equivalent Responsibilities
Define and architect digital subsystems within RFICs Partition functionality between analog, mixed‑signal, and digital domains to optimize performance, area, and power Develop subsystem‑level digital specifications in collaboration with RF, analog, and systems teams Own register/memory maps, digital interfaces, and configuration settings, diagnostic / test profiles Own the digital design and ensure design meets PVT, reliability, and automotive quality standards (FuSa, AEC‑Q100, ISO 26262) Support synthesis, STA, clock‑domain crossing, low‑power design, and DFT with physical design teams Ensure robustness across PVT, ESD, reliability, and automotive qualification corners (if applicable) Review ECOs, timing fixes, and power optimization strategies Lead activities for the design and implement high‑performance, low‑power analog and mixed‑signal blocks e.g. bandgap references, temperature sensors, diagnostic ADCs, programmable gain amplifiers, power detectors, bias circuits Derive block‑level specifications from system requirements and contribute to architecture discussions Own schematic design, pre‑/post‑layout simulation, and verification using industry‑standard EDA tools Collaborate with layout engineers to ensure robust and efficient physical design Support silicon bring‑up, validation, and debug in the lab Partner with RF, digital, and systems engineers to enable seamless integration of mixed‑signal IP into the overall sensor SoC Bonus: prior exposure to sensor products, or radar‑based systems Benefits
Medical insurance Vision insurance 401(k) Pension plan Paid paternity leave Paid maternity leave Tuition assistance San Jose, CA $80,000.00-$110,000.00 5 days ago Sunnyvale, CA $118,000.00-$170,000.00 2 weeks ago
#J-18808-Ljbffr