SPACE EXPLORATION TECHNOLOGIES CORP
Physical Design Engineer II (Silicon Engineering)
SPACE EXPLORATION TECHNOLOGIES CORP, Bastrop, Texas, United States, 78602
Physical Design Engineer II (Silicon Engineering)
Bastrop, TX | SpaceX
SpaceX is developing technologies to enable human life on Mars. We are building the Starlink broadband network and are looking for engineers to design next‑generation ASICs for space and ground infrastructures.
RESPONSIBILITIES
Perform partition synthesis and physical implementation steps (synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks).
Develop and improve physical design methodologies and automation scripts for various implementation steps.
Collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs.
Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution.
Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop.
QUALIFICATIONS
Bachelor’s degree in electrical engineering, computer engineering or computer science.
3+ years of professional experience in RTL2GDSII physical design and/or physical design flow development.
PREFERRED SKILLS AND EXPERIENCE
Experience with industry‑standard EDA tools and understanding of their underlying algorithms.
Knowledge of deep sub‑micron FinFET and CMOS solid‑state physics.
Understanding of CMOS digital design principles, standard‑cell functionality and libraries.
Understanding of CMOS power dissipation in deep sub‑micron processes (leakage/dynamic).
Familiarity with CMOS analog circuit and physical design.
Basic knowledge of DFT/Scan/MBIST/LBIST and its impact on physical design flows.
Self‑driven individual with a can‑do attitude, willing to learn and a team player.
ADDITIONAL REQUIREMENTS
Must be willing to work extended hours and weekends as needed.
To comply with U.S. Government export regulations, applicants must be a (i) U.S. citizen or national, (ii) U.S. lawful permanent resident (green card holder), (iii) refugee, or (iv) asylee, or be eligible to obtain required authorizations from the U.S. Department of State.
EEO STATEMENT SpaceX is an Equal Opportunity Employer; employment is based on merit, competence and qualifications and will not be influenced by race, color, religion, gender, national origin, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
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SpaceX is developing technologies to enable human life on Mars. We are building the Starlink broadband network and are looking for engineers to design next‑generation ASICs for space and ground infrastructures.
RESPONSIBILITIES
Perform partition synthesis and physical implementation steps (synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks).
Develop and improve physical design methodologies and automation scripts for various implementation steps.
Collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs.
Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution.
Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop.
QUALIFICATIONS
Bachelor’s degree in electrical engineering, computer engineering or computer science.
3+ years of professional experience in RTL2GDSII physical design and/or physical design flow development.
PREFERRED SKILLS AND EXPERIENCE
Experience with industry‑standard EDA tools and understanding of their underlying algorithms.
Knowledge of deep sub‑micron FinFET and CMOS solid‑state physics.
Understanding of CMOS digital design principles, standard‑cell functionality and libraries.
Understanding of CMOS power dissipation in deep sub‑micron processes (leakage/dynamic).
Familiarity with CMOS analog circuit and physical design.
Basic knowledge of DFT/Scan/MBIST/LBIST and its impact on physical design flows.
Self‑driven individual with a can‑do attitude, willing to learn and a team player.
ADDITIONAL REQUIREMENTS
Must be willing to work extended hours and weekends as needed.
To comply with U.S. Government export regulations, applicants must be a (i) U.S. citizen or national, (ii) U.S. lawful permanent resident (green card holder), (iii) refugee, or (iv) asylee, or be eligible to obtain required authorizations from the U.S. Department of State.
EEO STATEMENT SpaceX is an Equal Opportunity Employer; employment is based on merit, competence and qualifications and will not be influenced by race, color, religion, gender, national origin, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
#J-18808-Ljbffr