Senior ASIC Physical Design Engineer - Place & Route (Austin)

A leading semiconductor foundry in Austin, TX is seeking a Senior Engineer, Physical Design (ASIC/SoC Place & Route). This role involves the entire APR implementation flow from RTL-to-GDS, working in a hybrid model with 4 days in the office. Candidates should have a Master’s in Electrical/Computer Science Engineering and 7+ years of industry experience, particularly with TSMC technologies. The offered compensation ranges from $106,500 to $162,000 annually, along with comprehensive benefits. #J-18808-Ljbffr