ACL Digital
Responsibilities
Full chip and Block constraints development and constraints generation. Full chip and Block Synthesis, STA and timing closure using Primetime and DMSA flow. Run and debug Formality and VCLP Tools. Interfacing with internal and external teams including Design, IP, Library. Methodology & Flow development of Synthesis, Formality, STA & Timing Closure. Working independently with the PNR & RTL design team on Physical implementation and Power-intent requirements. Location
Senior Design Engineer – San Francisco, CA, United States
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Full chip and Block constraints development and constraints generation. Full chip and Block Synthesis, STA and timing closure using Primetime and DMSA flow. Run and debug Formality and VCLP Tools. Interfacing with internal and external teams including Design, IP, Library. Methodology & Flow development of Synthesis, Formality, STA & Timing Closure. Working independently with the PNR & RTL design team on Physical implementation and Power-intent requirements. Location
Senior Design Engineer – San Francisco, CA, United States
#J-18808-Ljbffr