Emulation Design Engineer — Chip Verification & Post-Silicon

A leading technology firm in San Jose is seeking a Design Engineer for their Emulation team. The role involves taking Cadence Palladium system chips from emulation to production, focusing on chip design verification and supporting software integration. Applicants should be currently enrolled in a relevant engineering degree program and possess experience with ASIC and hardware development. This position offers a competitive salary and comprehensive benefits. #J-18808-Ljbffr