Senior Static Timing Analysis Engineer (ASICs/FPGA)

A leading aerospace manufacturer in El Segundo, CA is seeking an experienced Static Timing Analysis Engineer to join its Electronic Products team. The role involves handling pre-layout and post-layout timing for cutting-edge digital ICs and FPGAs, collaborating for design closure, and working with various teams to achieve timing convergence. Candidates should have a Bachelor’s degree in Engineering and substantial experience in timing closure on ASICs. This position offers a competitive salary and opportunities for professional growth. #J-18808-Ljbffr