Intel Corporation
# **Welcome!**## .Senior Design Verification Engineer page is loaded## Senior Design Verification Engineerlocations:
US, California, Santa Claratime type:
Full timeposted on:
Posted Yesterdayjob requisition id:
JR0279202# **Job Details:**## Job Description:Intel is seeking a highly technical Senior Design Verification Engineer. In this senior technical leadership role, you will design and deliver next-generation chassis IPs, designed to scale across multiple product families. You will establish verification strategy and methodology, drive technical development with deep expertise, and deliver first-pass silicon success through best-in-class IP design and verification practices. This role requires exceptional technical depth across advanced DV methodologies and tools, combined with strong expertise in interconnect protocols, cache coherency, memory architecture, and software integration. You will be a key technical authority, owning multiple high-impact IP blocks and setting standards for technical excellence.**Responsibilities*** Design, develop, and deliver a comprehensive verification strategy and methodology that scales seamlessly from IP through subsystems to SoC-level verification* Design and implement advanced verification environments, tools, and test plans enabling first-pass silicon success; develop sophisticated testbenches, checkers, VIPs, and complex behavioral models* Collaborate closely with architecture, design, and software teams from initial product definition and specification reviews through implementation, bring up, and productization phases; balance complexity and ensure timely, high-quality execution* Drive ownership of multiple critical blocks and verification components; take full responsibility for functional signoffs and achievement of performance and power metrics* Lead IP delivery to multiple customers while ensuring technical excellence; balance competing requirements, schedules, and resources across teams* Champion innovation across simulation, formal, and accelerated verification methodologies; develop and evaluate new ML-based flows and hybrid software frameworks* Mentor and develop verification engineers; establish verification best practices and drive organizational technical excellenceThe candidate should exhibit the following behavioral traits:* Excellent communication and organizational skills with a proven track record of delivering on-time, high-quality silicon and establishing technical standards## **Qualifications:****Minimum Qualifications*** BS/MS in Electrical Engineering, Computer Science, or related field, with 12+ years of combined experience in:* Design verification; extensive background in IP DV with significant, demonstrated experience in subsystem and SoC-level verification* Interconnects, caches, and memory subsystems, including multiple bus protocols such as AMBA (CHI, ACE, AXI), PCIe, UCIe, and CXL; cache coherency and memory consistency models* Verification of global functions including debug, trace, clock & power management, RAS, QoS, and security features* Simulation-based verification methodologies including UVM, ABV, and co-simulation; proficiency in low-power verification techniques, HDL/verification languages, and industry-standard EDA tools* Coding proficiency across System Verilog/UVM, software programming languages (C/C++), scripting (Python), and build systems; established track record of developing and delivering highly configurable and reusable verification collateral## Job Type:Experienced Hire## Shift:Shift 1 (United States of America)## Primary Location:US, California, Santa Clara## Additional Locations:## Business group:Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society.## Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of TrustN/A**Benefits:**We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.
Find more information about all of our Amazing Benefits here:Annual Salary Range for jobs which could be performed in the US: $190,610.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.**Work Model for this Role**This role will require an on-site presence. \* Job posting details (such as work model, location or time type) are subject to change. #J-18808-Ljbffr
US, California, Santa Claratime type:
Full timeposted on:
Posted Yesterdayjob requisition id:
JR0279202# **Job Details:**## Job Description:Intel is seeking a highly technical Senior Design Verification Engineer. In this senior technical leadership role, you will design and deliver next-generation chassis IPs, designed to scale across multiple product families. You will establish verification strategy and methodology, drive technical development with deep expertise, and deliver first-pass silicon success through best-in-class IP design and verification practices. This role requires exceptional technical depth across advanced DV methodologies and tools, combined with strong expertise in interconnect protocols, cache coherency, memory architecture, and software integration. You will be a key technical authority, owning multiple high-impact IP blocks and setting standards for technical excellence.**Responsibilities*** Design, develop, and deliver a comprehensive verification strategy and methodology that scales seamlessly from IP through subsystems to SoC-level verification* Design and implement advanced verification environments, tools, and test plans enabling first-pass silicon success; develop sophisticated testbenches, checkers, VIPs, and complex behavioral models* Collaborate closely with architecture, design, and software teams from initial product definition and specification reviews through implementation, bring up, and productization phases; balance complexity and ensure timely, high-quality execution* Drive ownership of multiple critical blocks and verification components; take full responsibility for functional signoffs and achievement of performance and power metrics* Lead IP delivery to multiple customers while ensuring technical excellence; balance competing requirements, schedules, and resources across teams* Champion innovation across simulation, formal, and accelerated verification methodologies; develop and evaluate new ML-based flows and hybrid software frameworks* Mentor and develop verification engineers; establish verification best practices and drive organizational technical excellenceThe candidate should exhibit the following behavioral traits:* Excellent communication and organizational skills with a proven track record of delivering on-time, high-quality silicon and establishing technical standards## **Qualifications:****Minimum Qualifications*** BS/MS in Electrical Engineering, Computer Science, or related field, with 12+ years of combined experience in:* Design verification; extensive background in IP DV with significant, demonstrated experience in subsystem and SoC-level verification* Interconnects, caches, and memory subsystems, including multiple bus protocols such as AMBA (CHI, ACE, AXI), PCIe, UCIe, and CXL; cache coherency and memory consistency models* Verification of global functions including debug, trace, clock & power management, RAS, QoS, and security features* Simulation-based verification methodologies including UVM, ABV, and co-simulation; proficiency in low-power verification techniques, HDL/verification languages, and industry-standard EDA tools* Coding proficiency across System Verilog/UVM, software programming languages (C/C++), scripting (Python), and build systems; established track record of developing and delivering highly configurable and reusable verification collateral## Job Type:Experienced Hire## Shift:Shift 1 (United States of America)## Primary Location:US, California, Santa Clara## Additional Locations:## Business group:Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society.## Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of TrustN/A**Benefits:**We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.
Find more information about all of our Amazing Benefits here:Annual Salary Range for jobs which could be performed in the US: $190,610.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.**Work Model for this Role**This role will require an on-site presence. \* Job posting details (such as work model, location or time type) are subject to change. #J-18808-Ljbffr