Senior Static Timing Analysis Engine Architect

A leading semiconductor company seeks an experienced Senior Static Timing Analysis (STA) Developer in San Jose, California. You will architect and optimize next-generation timing analysis engines for ASIC and FPGA design flows. Key responsibilities include developing high-performance STA engines, optimizing performance, and ensuring robustness during customer tape-outs. This role requires over 10 years of EDA software experience, strong C/C++ skills, and a deep understanding of static timing analysis algorithms. The salary range is $178.9K - $259.0K USD depending on experience. #J-18808-Ljbffr