Intel Corporation
# **Welcome!**## .Clocking Design Engineer page is loaded## Clocking Design Engineerlocations:
US, Texas, Austin:
US, Oregon, Hillsborotime type:
Full timeposted on:
Posted Todaytime left to apply:
End Date: April 8, 2026 (30+ days left to apply)job requisition id:
JR0279530# **Job Details:**## Job Description:We are seeking a highly skilled Clocking Design Engineer to join our dynamic team.You will be part of the clock team supporting Intel’s flagship CPU designs in the most advanced process nodes. In this role, you will be involved in clocking architecture definition, design and implementation of custom clock global network, development of clock tree synthesis flow, as well as custom clock circuit design and clock library cell design.This is a cross-functional role that requires interfacing and collaborating with other teams such as architecture, physical design, full chip integration, RTL, circuits, validation, design automation team and EDA vendors, in a high-paced atmosphere.**Key Responsibilities:*** Implement custom clock distribution network for high frequency flagship CPU designs* Develop clock tree synthesis flow and deliver custom clock solutions for high frequency flagship CPU designs* Design custom circuits and library cells related to clock distribution## **Qualifications:**You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.**Minimum Qualifications:*** Bachelor´s degree in electrical engineering, computer engineering related STEM field and 4+ years of experience and/or Master´s degree and 3+ years of experience and/or PhD and 2+ years of experience, during which the candidate has demonstrated experience in:
+ Physical design and advanced process technologies and circuit implementation
+ Static timing analysis, clock tree synthesis, and clock-related timing parameters
+ Use of industry-standard scripting and automation within EDA tool flows**Preferred Qualifications:*** 3+ years of experience in:
+ Backend design and/or integration on leading edge process nodes
+ High frequency clock distribution design and implementation, custom circuits and clock tree synthesis## Job Type:Experienced Hire## Shift:Shift 1 (United States of America)## Primary Location:US, Texas, Austin## Additional Locations:US, Oregon, Hillsboro## Business group:Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.## Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of TrustN/A## BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the .Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.**Work Model for this Role**This role will require an on-site presence. \* Job posting details (such as work model, location or time type) are subject to change. #J-18808-Ljbffr
US, Texas, Austin:
US, Oregon, Hillsborotime type:
Full timeposted on:
Posted Todaytime left to apply:
End Date: April 8, 2026 (30+ days left to apply)job requisition id:
JR0279530# **Job Details:**## Job Description:We are seeking a highly skilled Clocking Design Engineer to join our dynamic team.You will be part of the clock team supporting Intel’s flagship CPU designs in the most advanced process nodes. In this role, you will be involved in clocking architecture definition, design and implementation of custom clock global network, development of clock tree synthesis flow, as well as custom clock circuit design and clock library cell design.This is a cross-functional role that requires interfacing and collaborating with other teams such as architecture, physical design, full chip integration, RTL, circuits, validation, design automation team and EDA vendors, in a high-paced atmosphere.**Key Responsibilities:*** Implement custom clock distribution network for high frequency flagship CPU designs* Develop clock tree synthesis flow and deliver custom clock solutions for high frequency flagship CPU designs* Design custom circuits and library cells related to clock distribution## **Qualifications:**You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.**Minimum Qualifications:*** Bachelor´s degree in electrical engineering, computer engineering related STEM field and 4+ years of experience and/or Master´s degree and 3+ years of experience and/or PhD and 2+ years of experience, during which the candidate has demonstrated experience in:
+ Physical design and advanced process technologies and circuit implementation
+ Static timing analysis, clock tree synthesis, and clock-related timing parameters
+ Use of industry-standard scripting and automation within EDA tool flows**Preferred Qualifications:*** 3+ years of experience in:
+ Backend design and/or integration on leading edge process nodes
+ High frequency clock distribution design and implementation, custom circuits and clock tree synthesis## Job Type:Experienced Hire## Shift:Shift 1 (United States of America)## Primary Location:US, Texas, Austin## Additional Locations:US, Oregon, Hillsboro## Business group:Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.## Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of TrustN/A## BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the .Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.**Work Model for this Role**This role will require an on-site presence. \* Job posting details (such as work model, location or time type) are subject to change. #J-18808-Ljbffr