Neurophos
Join to apply for the
VP of Engineering, VLSI
role at
Neurophos
At Neurophos, listed as one of EE Times’ 2025 100 Most Promising Start‑ups, we are revolutionizing AI computation with the world’s first metamaterial‑based optical computing platform. Our design addresses the traditional shortcoming of silicon photonics for inference and provides an unprecedented AI engine with substantially higher throughput and efficiency than any existing solution.
We’ve created an optical metasurface with 10,000× the density of traditional silicon photonics modulators. This enables a solution with 100× gains in power efficiency for neural network computing without sacrificing throughput; we’ve made improvements there, too. By integrating metamaterials with conventional optoelectronics, our compute‑in‑memory optical system surpasses existing solutions by a wide margin and enables truly high‑performance and cost‑effective AI compute.
Join us to shape the future of optical computing.
Location:
Austin, TX or San Francisco, CA. Full‑time onsite position.
Position Overview We are seeking a Vice President of VLSI to provide strategic and hands‑on technical leadership for the design, development, and high‑volume production of complex mixed‑signal ASICs that drive and control our ultra‑high‑performance Optical Processing Units. This executive role will lead the growth and scaling of our VLSI organization (digital, analog, mixed‑signal, and FPGA teams), own the full VLSI design lifecycle, and ensure seamless integration with our data centre partners. The ideal candidate is a technically rigorous leader with extensive experience shipping sophisticated data centre ICs featuring high‑speed photonic interfaces (>50 Gbaud) and who thrives in a fast‑paced startup environment.
Key Responsibilities
Provide strategic vision and rigorous technical leadership for the VLSI organization, defining and executing the ASIC roadmap in tight alignment with Neurophos’ optical computing architecture and product milestones.
Build, mentor, and scale world‑class digital, analog/mixed‑signal, and FPGA engineering teams; lead hiring, onboarding, and talent development.
Define and implement a quality‑driven design methodology, including best practices and project‑development processes, in alignment with the other organization at Neurophos.
Oversee end‑to‑end ASIC development: architecture, design, verification, physical design, tape‑out, validation, and transfer to high‑volume manufacturing.
Drive the design of complex mixed‑signal SoCs with substantial digital and mixed‑signal complexity, including ultra‑high‑speed SerDes/data interfaces and driver circuitry for silicon photonics electro‑optical modulators and fast detectors.
Optimize performance, power, and area (PPA) for AI compute workloads while ensuring robust signal and power integrity in co‑packaged optics environments.
Manage in‑house design, outsourced design partners, and hybrid execution models to meet aggressive timelines.
Negotiate, license, and integrate third‑party IP (CPU cores, high‑speed SerDes, memory controllers, etc.).
Establish and maintain strong relationships with leading CMOS foundries and drive successful on‑time tape‑outs on advanced nodes.
Negotiate and support enterprise‑wide EDA tool licenses and flows.
Lead DFM/DFT to achieve high yield and reliability at scale.
Collaborate closely with the silicon photonics, packaging, firmware, and system architecture teams to deliver fully integrated optical compute modules.
Work closely with program managers to plan program schedules, required resources, identify critical paths, and effectively communicate progress‑to‑plan.
Contribute to intellectual property strategy and patent filings related to VLSI architectures, high‑speed electrical‑optical interfaces, and mixed‑signal architectures.
Manage department budget, vendor relationships, and resource allocation while fostering a culture of technical excellence and innovation.
Qualifications
PhD or MS in Electrical Engineering, Computer Engineering, or related field (PhD preferred).
Minimum 15 years of industry experience in VLSI/ASIC design and productisation, with at least 7 years in senior technical leadership roles managing large digital + analog teams.
Proven track record of bringing complex data centre‑class mixed‑signal SoCs to high‑volume production (≥2 full cycles on ≤7 nm nodes strongly preferred).
Direct hands‑on experience designing ASICs that drive and interface with high‑speed (≥56 Gbaud) silicon photonic devices (modulators, detectors, TIAs).
Deep expertise in high‑speed mixed‑signal design, including fast SerDes, HBM interfaces, CDR, and signal/power integrity in multi‑chip modules.
Extensive experience working with top‑tier CMOS foundries, managing PDKs, tape‑outs, and yield improvement.
Demonstrated success in negotiating and integrating third‑party IP and managing enterprise EDA tool flows and contracts.
Strong background in DFM, DFT, reliability, and production test for advanced‑node mixed‑signal chips.
Prior success building and scaling high‑performing VLSI organisations in startup or fast‑growth environments.
Preferred Skills
Prior leadership of VLSI teams that delivered chips for optical computing or optical networking, silicon photonics‑based data centre switches, or linear pluggable optics (LPO).
Hands‑on experience with co‑packaged optics (CPO) integration and related technologies.
Knowledge of compute‑in‑memory architectures or optical neural network accelerators.
What We Offer
A pivotal role in an innovative startup redefining the future of AI hardware.
A collaborative and intellectually stimulating work environment.
Competitive compensation, including salary and equity options.
Opportunities for career growth and future team leadership.
Access to cutting‑edge technology and state‑of‑the‑art facilities.
Opportunity to publish research and contribute to the field of efficient AI inference.
If you are passionate about pushing the boundaries of model optimisation and driving impact in the semiconductor industry, we want to hear from you! This is a rare opportunity to work on a game‑changing technology at the intersection of photonics and AI. As part of our elite team, you’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Be a key player in bringing this transformative innovation to the world.
#J-18808-Ljbffr
VP of Engineering, VLSI
role at
Neurophos
At Neurophos, listed as one of EE Times’ 2025 100 Most Promising Start‑ups, we are revolutionizing AI computation with the world’s first metamaterial‑based optical computing platform. Our design addresses the traditional shortcoming of silicon photonics for inference and provides an unprecedented AI engine with substantially higher throughput and efficiency than any existing solution.
We’ve created an optical metasurface with 10,000× the density of traditional silicon photonics modulators. This enables a solution with 100× gains in power efficiency for neural network computing without sacrificing throughput; we’ve made improvements there, too. By integrating metamaterials with conventional optoelectronics, our compute‑in‑memory optical system surpasses existing solutions by a wide margin and enables truly high‑performance and cost‑effective AI compute.
Join us to shape the future of optical computing.
Location:
Austin, TX or San Francisco, CA. Full‑time onsite position.
Position Overview We are seeking a Vice President of VLSI to provide strategic and hands‑on technical leadership for the design, development, and high‑volume production of complex mixed‑signal ASICs that drive and control our ultra‑high‑performance Optical Processing Units. This executive role will lead the growth and scaling of our VLSI organization (digital, analog, mixed‑signal, and FPGA teams), own the full VLSI design lifecycle, and ensure seamless integration with our data centre partners. The ideal candidate is a technically rigorous leader with extensive experience shipping sophisticated data centre ICs featuring high‑speed photonic interfaces (>50 Gbaud) and who thrives in a fast‑paced startup environment.
Key Responsibilities
Provide strategic vision and rigorous technical leadership for the VLSI organization, defining and executing the ASIC roadmap in tight alignment with Neurophos’ optical computing architecture and product milestones.
Build, mentor, and scale world‑class digital, analog/mixed‑signal, and FPGA engineering teams; lead hiring, onboarding, and talent development.
Define and implement a quality‑driven design methodology, including best practices and project‑development processes, in alignment with the other organization at Neurophos.
Oversee end‑to‑end ASIC development: architecture, design, verification, physical design, tape‑out, validation, and transfer to high‑volume manufacturing.
Drive the design of complex mixed‑signal SoCs with substantial digital and mixed‑signal complexity, including ultra‑high‑speed SerDes/data interfaces and driver circuitry for silicon photonics electro‑optical modulators and fast detectors.
Optimize performance, power, and area (PPA) for AI compute workloads while ensuring robust signal and power integrity in co‑packaged optics environments.
Manage in‑house design, outsourced design partners, and hybrid execution models to meet aggressive timelines.
Negotiate, license, and integrate third‑party IP (CPU cores, high‑speed SerDes, memory controllers, etc.).
Establish and maintain strong relationships with leading CMOS foundries and drive successful on‑time tape‑outs on advanced nodes.
Negotiate and support enterprise‑wide EDA tool licenses and flows.
Lead DFM/DFT to achieve high yield and reliability at scale.
Collaborate closely with the silicon photonics, packaging, firmware, and system architecture teams to deliver fully integrated optical compute modules.
Work closely with program managers to plan program schedules, required resources, identify critical paths, and effectively communicate progress‑to‑plan.
Contribute to intellectual property strategy and patent filings related to VLSI architectures, high‑speed electrical‑optical interfaces, and mixed‑signal architectures.
Manage department budget, vendor relationships, and resource allocation while fostering a culture of technical excellence and innovation.
Qualifications
PhD or MS in Electrical Engineering, Computer Engineering, or related field (PhD preferred).
Minimum 15 years of industry experience in VLSI/ASIC design and productisation, with at least 7 years in senior technical leadership roles managing large digital + analog teams.
Proven track record of bringing complex data centre‑class mixed‑signal SoCs to high‑volume production (≥2 full cycles on ≤7 nm nodes strongly preferred).
Direct hands‑on experience designing ASICs that drive and interface with high‑speed (≥56 Gbaud) silicon photonic devices (modulators, detectors, TIAs).
Deep expertise in high‑speed mixed‑signal design, including fast SerDes, HBM interfaces, CDR, and signal/power integrity in multi‑chip modules.
Extensive experience working with top‑tier CMOS foundries, managing PDKs, tape‑outs, and yield improvement.
Demonstrated success in negotiating and integrating third‑party IP and managing enterprise EDA tool flows and contracts.
Strong background in DFM, DFT, reliability, and production test for advanced‑node mixed‑signal chips.
Prior success building and scaling high‑performing VLSI organisations in startup or fast‑growth environments.
Preferred Skills
Prior leadership of VLSI teams that delivered chips for optical computing or optical networking, silicon photonics‑based data centre switches, or linear pluggable optics (LPO).
Hands‑on experience with co‑packaged optics (CPO) integration and related technologies.
Knowledge of compute‑in‑memory architectures or optical neural network accelerators.
What We Offer
A pivotal role in an innovative startup redefining the future of AI hardware.
A collaborative and intellectually stimulating work environment.
Competitive compensation, including salary and equity options.
Opportunities for career growth and future team leadership.
Access to cutting‑edge technology and state‑of‑the‑art facilities.
Opportunity to publish research and contribute to the field of efficient AI inference.
If you are passionate about pushing the boundaries of model optimisation and driving impact in the semiconductor industry, we want to hear from you! This is a rare opportunity to work on a game‑changing technology at the intersection of photonics and AI. As part of our elite team, you’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Be a key player in bringing this transformative innovation to the world.
#J-18808-Ljbffr